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| mas 35x9f mpeg layer 2/3, aac audio decoder, g.729 annex a codec june 30, 2004 6251-505-1ds d a t a s h e e t m i c r o n a s m i c r o n a s
2 june 30, 2004; 6251-505-1ds micronas contents page section title mas 35x9f data sheet 5 1. introduction 61.1.features 6 1.2. features of the mas 35x9f family 7 1.3. application overview 8 2. functional description 8 2.1. overview 8 2.2. architecture of the mas 35x9f 8 2.3. dsp core 9 2.3.1. ram and registers 9 2.3.2. firmware and software 9 2.3.2.1. internal program rom and firmware, mpeg-decoding 9 2.3.2.2. program download feature 10 2.4. audio codec 10 2.4.1. a/d converter and microphone amplifier 10 2.4.2. baseband processing 10 2.4.2.1. bass, treble, and loudness 10 2.4.2.2. micronas bass (mb) 10 2.4.2.3. automatic volume control (avc) 10 2.4.2.4. balance and volume 11 2.4.3. d/a converters 11 2.4.4. output amplifiers 11 2.5. clock management 11 2.5.1. dsp clock 11 2.5.2. clock output at clko 12 2.6. power supply concept 12 2.6.1. power supply regions 12 2.6.2. dc/dc converters 13 2.6.3. power supply configurations 15 2.7. mp3 block input mode 15 2.7.1. functional description of the mp3 block input mode 16 2.7.2. setup 16 2.7.2.1. resync timeout 16 2.7.2.2. detailed setup 16 2.8. battery voltage supervision 16 2.9. interfaces 16 2.9.1. i2c control interface 16 2.9.2. s/pdif input interface 16 2.9.3. s/pdif output 17 2.9.4. multiline serial audio input (sdi, sdib) 17 2.9.5. multiline serial output (sdo) 17 2.9.6. parallel input/output interface (pio) 17 2.10. mpeg synchronization output 18 2.11. default operation 18 2.11.1. stand-by functions 18 2.11.2. power-up of the dc/dc converters and reset 19 2.11.2.1. important advice for turn-on and operating voltage contents, continued page section title micronas june 30, 2004; 6251-505-1ds 3 data sheet mas 35x9f 20 2.11.3. reset signal specification 21 2.11.4. control of the signal processing 21 2.11.5. start-up of the audio codec 21 2.11.6. power-down 22 3. controlling 22 3.1. i 2 c interface 22 3.1.1. device address 22 3.1.2. i 2 c registers and subaddresses 22 3.1.3. naming convention 22 3.2. direct configuration registers 23 3.2.1. write direct configuration registers 23 3.2.2. read direct configuration register 28 3.3. dsp core 28 3.3.1. access protocol 29 3.3.2. data formats 29 3.3.2.1. run and freeze (codes 0hex to 3hex) 29 3.3.2.2. read register (code a hex ) 29 3.3.2.3. write register (code b hex ) 30 3.3.2.4. read memory (codes c hex and d hex ) 30 3.3.2.5. short read memory (codes c4 hex and d4 hex ) 30 3.3.2.6. write memory (codes ehex and fhex) 30 3.3.2.7. short write memory (codes e4 hex and f4 hex ) 30 3.3.2.8. clear sync signal (code 5hex) 31 3.3.2.9. default read 31 3.3.2.10. fast program download (code 6 hex ) 31 3.3.2.11. serial program download 32 3.3.2.12. read ic version (code 7 hex ) 32 3.3.3. list of dsp registers 32 3.3.4. list of dsp memory cells 33 3.3.4.1. application selection and application running 33 3.3.4.2. application specific control 43 3.3.5. ancillary data 43 3.3.6. reading of the memory cells ?number of bits in ancillary data? and ?ancillary data? 44 3.3.7. dsp volume control 44 3.3.8. explanation of the g.729a data format 45 3.4. audio codec access protocol 45 3.4.1. write codec register 45 3.4.2. read codec register 46 3.4.3. codec registers 52 3.4.4. basic mb configuration 4 june 30, 2004; 6251-505-1ds micronas contents, continued page section title mas 35x9f data sheet 53 4. specifications 53 4.1. outline dimensions 56 4.2. pin connections and short descriptions 59 4.3. pin descriptions 59 4.3.1. power supply pins 59 4.3.2. analog reference pins 59 4.3.3. dc/dc converters and battery voltage supervision 59 4.3.4. oscillator pins and clocking 59 4.3.5. control lines 59 4.3.6. parallel interface lines 60 4.3.6.1. pio handshake lines 60 4.3.7. serial input interface (sdi) 60 4.3.8. serial input interface b (sdib) 60 4.3.9. serial output interface (sdo) 60 4.3.10. s/pdif input interface 60 4.3.11. s/pdif output interface 60 4.3.12. analog input interfaces 60 4.3.13. analog output interfaces 61 4.3.14. miscellaneous 61 4.4. pin configuration 62 4.5. internal pin circuits 63 4.5.1. reset pin configuration for mas 3529f and mas 3539f 64 4.6. electrical characteristics 64 4.6.1. absolute maximum ratings 66 4.6.1.1. recommended operating conditions 69 4.6.2. digital characteristics 70 4.6.2.1. i 2 c characteristics 71 4.6.2.2. serial (i 2 s) input interface characteristics (sdi, sdib) 72 4.6.2.3. serial output interface characteristics (sdo) 74 4.6.2.4. s/pdif input characteristics 75 4.6.2.5. s/pdif output characteristics 75 4.6.2.6. pio as parallel input interface: dma mode 77 4.6.2.7. pio as parallel input interface: program download mode 78 4.6.2.8. pio as parallel output interface 79 4.6.3. analog characteristics 82 4.6.4. dc/dc converter characteristics 84 4.6.5. typical performance characteristics 87 5. application 87 5.1. typical application in a portable player 88 5.2. recommended dc/dc converter application circuit 90 6. data sheet history data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 5 mpeg layer 2/3, aac audio decoder, g.729 annex a codec release note: revision bars indicate significant changes to the previous edition. this data sheet applies to the mas 35x9f version b4. 1. introduction the mas 35x9f is a single-chip, low-power mpeg layer 2/3 and mpeg2-aac audio stereo decoder. it also contains the g.729 annex a speech compression and decompression technology for use in memory- based or broadcast applicati ons. additional functional- ity is achievable via download software (e.g., celp voice decoder, micronas sc4 (adpcm) encoder/ decoder). the mas 35x9f decoding block accepts compressed digital data streams as serial bit streams or in parallel format, and provides serial pcm and s/pdif output of decompressed audio. in addition to the signal process- ing function, the ic incorporates a high-performance stereo d/a converter, headphone amplifiers, a stereo a/d converter, a microphone amplifier, and two dc/dc converters. thus, the mas 35x9f provides a true ?all-in-one? solution that is ideally su ited for highly optimized mem- ory-based portable music players with integrated speech recording and playback function. in mpeg 1 (iso 11172-3), three hierarchical layers of compression have been standardized. the most sophisticated and complex, layer 3, allows compres- sion rates of approximately 12:1 for mono and stereo signals while still maintainin g cd audio quality. layer 2 (widely used, e.g., in dvd) achieves a compression of 8:1 without significant losses in audio quality. the mas 35x9f supports the ?advanced audio cod- ing? (aac) that is defined as a part of mpeg 2. aac provides compression rates up to 16:1. it defines sev- eral profiles for different applications. this ic decodes the ?low complexity profile? that is especially optimized for portable applications. the mas 35x9f also implements a voice encoder and decoder that is compliant to the itu standard g.729 annex a. sc4 is a proprietary micronas speech codec technol- ogy that can be downloaded to the mas 35x9f, to allow recording and playing back speech at various sampling rates. mas 35x9f data sheet 6 june 30, 2004; 6251-505-1ds micronas 1.1. features firmware ? mpeg 1/2 layer 2 and layer 3 decoder ? extension to mpeg 2 layer 3 for low sampling rates (?mpeg 2.5?) ? extraction of mpeg ancillary data ? mpeg 2 aac decoder (low-complexity profile) ? micronas g.729 annex a speech compression and decompression ? master or slave clock operation ? adaptive bit rates (bit rate switching) ? intelligent power manageme nt (processor clock is dependent on sampling frequencies) ? sdmi-compliant security technology ? stereo channel mixer ? bass, treble, and loudness function ? micronas bass (mb) ? automatic volume control (avc) interfaces ? two serial asynchronous interfaces for bit streams and uncompressed digital audio ? parallel handshake bit stream input ? serial audio output via i 2 s and related formats ? s/pdif data input and output ? controlling via i 2 c interface hardware features ? two independent embedded dc/dc converters, (e.g., for dsp and flash ram supply) ? low dc/dc converter start-up voltage (0.9 v) ? dc converter efficiency up to 95% ? battery voltage monitor ? low supply voltage down to 2.2 v ? low power dissipation, e.g., 87 mw (128kbit/s, 44.1 khz, headphone playback) ? high-performance risc dsp core ? on-chip crystal oscillator ? hardware power management and power-off func- tions ? microphone amplifier ? stereo a/d converter for fm/am-radio and speech input ? cd quality stereo d/a converter ? headphone amplifier ? noise and power-optimized volume ? external clock or crystal frequency of 13...28 mhz ? standby current < 10 a 1.2. features of the mas 35x9f family feature 3509 3519 3529 3539 3549 3559 layer 3 decoder xxxx g.729 encoder/decoder x x x aac decoder x x x data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 7 1.3. application overview the following block diagram shows an example appli- cation for the mas 35x9f in a portable audio player device. besides a simple controller and the external flash memories, all required components are inte- grated in the mas 35x9f. the mas 35x9f supports both speech and radio quality audio encoding, as well as compressed-audio decoding tasks. fig. 1?1 depicts a portable power-optimized audio application. the two embedded dc/dc converters of the mas 35x9f generate optimum power supply volt- ages for the dsp core and also for state-of-the art flash memories that typically require 2.7 to 3.3 v sup- ply. the performance of the dc/dc converters reaches efficiencies of up to 95%. fig. 1?1: example of an application for the mas 35x9f in a portable audio player device mas 35x9f portable digital music player a/d microphone amplifier d/a headphone amplifier volume optional line in optional digital in s/pdif or serial crystal osc./pll dc/dc1 i 2 cdc/dc2 audio baseband features dsp core mp3 aac optional sc4 downloads headphone digital out s/pdif and serial system clock e.g. 2.2 v e.g. 3.0 v i 2 c control parallel i/o bus i 2 c flash ram mas 35x9f data sheet 8 june 30, 2004; 6251-505-1ds micronas 2. functional description 2.1. overview the mas 35x9f is intended for use in portable con- sumer audio applications. it receives parallel or serial data streams and decodes mpeg layer 2 and 3 (including the low sampling frequency extensions) and mpeg 2 aac. a low bit-rate speech codec, compliant to the itu standard g.729 annex a, is integrated. additional downloadable software modules (sdmi, other audio/speech encoders/decoders) are available on request. 2.2. architecture of the mas 35x9f the hardware of the mas 35x9f consists of a high- performance risc digital signal processor (dsp), and appropriate interfaces. a hardware overview of the ic is shown in fig. 2?1. 2.3. dsp core the internal processor is a dedicated dsp for advanced audio applications. fig. 2?1: the mas 35x9f architecture 2 dsp core audio codec mic. input (incl. bias) line input s/pdif input 1 s/pdif input 2 serial audio (i 2 s, sdi) serial audio (stream, sdib) v bat v1 v2 xtal 18.432 mhz clko parallel i/o bus (pio) i 2 c s/pdif output serial audio (i 2 s, sdo) audio output control alu mac accumulators rom d0 d1 registers div. input select output select a/d audio proc. d/a control dccf dcfr dsp codec volt. mon. i 2 c interface div. scaler osc. pll synth. dc/dc 2 dc/dc 1 synthesizer clock 1 2 2 mix data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 9 2.3.1. ram and registers the dsp core has access to two ram banks denoted d0 and d1. all ram addresses can be accessed in a 20-bit or a 16-bit mode via i 2 c bus. for fast access of internal dsp states the processor core has an address space of 256 data registers which also can be accessed via i 2 c bus. for more details, please refer to section 3.3. on page 28. 2.3.2. firmware and software 2.3.2.1. internal program rom and firmware, mpeg-decoding the firmware implemented in the program rom of the mas 35x9f provides mpeg 1/2 layer 2, mpeg 1/2/ 2.5 layer 3 and mpeg 2 aac-decoding as well as a g.729 encoder and decoder. the dsp operating system starts the firmware in the ?application selection mode?. by setting the appropri- ate bit in the applicatio n select memory cell (see table 3?9 on page 33), the mpeg audio decoder or the g.729 codec can be activated. the mpeg decoder provides an automatic standard detection mode. if all mpeg audio decoders are selected, the layer 2, layer 3 or aac bit stream is rec- ognized and decoded automatically. to add/remove mpeg layers while running in mpeg decoding mode (e.g. layer 2, layer 3 (0x0c) to layer 2, layer 3, aac (0x1c)), the application selec- tion has to be reset before writing the new value. for general control purposes, the operation system provides a set of i 2 c instructions that give access to internal dsp registers and memory areas. an auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. this matrix is capable of performing the balance control and a sim- ple kind of stereo basewidth enhancement. all four factors ll, lr, rl, and rr are adjustable, please refer to fig. 3?3 on page 44. 2.3.2.2. program download feature the standard functions of the mas 35x9f can be extended or substituted by downloading up to 4 kwords (1 word = 20 bits) of program code and additionally up to 4 kwords of coefficients into the internal ram. fig. 2?2: encoder signal flow fig. 2?3: decoder signal flow out a/d audio proc. d/a encoder mix pio sdi line in mic in out a/d audio proc. d/a decoder mix sdo s/pdif pio sdib line in dsp volume matrix mic in mas 35x9f data sheet 10 june 30, 2004; 6251-505-1ds micronas 2.4. audio codec a sophisticated set of audio converters and sound fea- tures has been implemented to comply with various kinds of operating environments that range up to high- end equipment (see fig. 2?4). fig. 2?4: signal flow block diagram of audio codec 2.4.1. a/d converter and microphone amplifier a pair of a/d converters is provided for recording or loop-through purposes. in addition, a microphone amplifier including voltage supply function for an elec- tret type microphone has been integrated. 2.4.2. baseband processing the several baseband functions are applied to the dig- ital audio signal immediately before d/a conversion. 2.4.2.1. bass, treble, and loudness standard baseband functions such as bass, treble, and loudness are provided (refer to table 3?16 for details). 2.4.2.2. micronas bass (mb) the micronas bass system (mb) was developed to extend the frequency range of loudspeakers or head- phones below the cutoff frequency of the speakers. apart from dynamically amplifying the low-frequency bass signals, the mb exploits the psycho-acoustic phe- nomenon of the ?missing fundamental?. adding har- monics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. due to the parametric implementation of the mb, it can be cus- tomized to create different bass effects and adapted to various loudspeaker characteristics (see section 3.4.4. and table 3?16). 2.4.2.3. automatic volume control (avc) in a collection of tracks from different sources fairly often the average volume level varies. especially in a noisy listening environment the user must adjust the volume to comfortably enjoy listening. the automatic volume correction (avc) solves this problem by equalizing the volume level. to prevent clipping, the avc's gain decreases quickly in dynamic boost conditions . to suppress oscillation effects, the gain increases rather slowly for low level inputs. the decay time is programmable by means of the avc register (see table 3?16 on page 46). for input levels of -18 dbr to 0 dbr, the avc maintains a fixed output level of -9 dbr. fig. 2?5 shows the avc output level versus its input level. for volume and baseband registers set to 0 db, a level of 0 dbr corre- sponds to full scale input/output. fig. 2?5: simplified avc characteristics 2.4.2.4. balance and volume to minimize quantization noise, the main volume con- trol is automatically split into a digital and an analog part. the volume range is ? audio codec mic-amplifier incl. bias dsp output mb headphone amplifier q-peak q-peak ? ? ? ? ? + ? ? ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 11 2.4.3. d/a converters one pair of micronas? unique multibit sigma-delta d/a converters is used to convert the audio data with high linearity and a superior s/n. in order to attenuate high- frequency noise caused by noise-shaping, internal low-pass filters are included. they require additional external capacitors between pins filtx and outx (see section 5.1. on page 87). 2.4.4. output amplifiers the integrated output amplifiers are capable of directly driving stereo headphones or loudspeakers of 16 to 32 ? ? fig. 2?6: bridge operation mode 2.5. clock management the mas 35x9f is driven by a single crystal-controlled clock with a frequency of 18.432 mhz. it is possible to drive the mas 35x9f with other reference clocks. in this case, the nominal crystal frequency must be writ- ten into memory location d0:348. the crystal clock acts as a reference for th e embedded synthesizer that generates the internal clock. for compressed audio data reception, the mas 35x9f may act either as the clock master (demand mode) or as a slave (broadcast mode) as defined by bit[1] in iocontrolmain memory cell (see table 3?9 on page 33). in both modes, the output of the clock syn- thesizer depends on the sample rate of the decoded data stream as shown in table 2?1. in the broadcast mode (pll on), the incoming audio data controls the clock synthesizer via a pll. in the demand mode (pll off) the mas 35x9f acts as the system master clock. the data transfer is trig- gered by a demand signal at pin eod . 2.5.1. dsp clock the dsp clock has a separate divider. in order to reduce the power consumption, it is set to the lowest acceptable rate of the synthesizer clock which is capa- ble to allow the processor core to perform all tasks. 2.5.2. clock output at clko if the dsp or audio codec functions are enabled (bits[11] or [10] in th e control register at i 2 c subad- dress 6a hex ), the reference clock at pin clko is derived from the synthesizer clock. dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clock- out by 1, 2, or 4, as shown in table 2?1. an additional division by 2 may be selected by setting bit[17] of the outclkconfig memory cell (see table 3?9 on page 33). the scaler can be disabled by setting bit[8] of this cell. the controlling at outclkco nfig is only possible as long as the dsp is operational (bit[10] of the control register). settings remain va lid if the dsp is disabled by clearing bit[10]. r ? table 2?1: settings of bits[8] and [17] in outclkconfig and resulting clko output frequencies f s /khz output frequency at clko/mhz synth. clock bit[8]=1 scaler on bit[8]=0, bit[17]=0 scaler plus extra division bit[8]=0, bit[17]=1 48 24.576 512 ? ? ? ? ? ? ? ? ? ? ? ? mas 35x9f data sheet 12 june 30, 2004; 6251-505-1ds micronas 2.6. power supply concept the mas 35x9f was designed for minimal power dis- sipation. in order to optimize the battery management in portable players, two dc/dc converters were imple- mented to supply the complete portable audio player with regulated voltages. 2.6.1. power supply regions the mas 35x9f has five power supply regions. the vdd/vss pin pair supplies all digital parts includ- ing the dsp core, the xvdd/xvss pin pair is con- nected to the digital signal pin output buffers, the avdd0/avss0 supply is for the analog output amplifi- ers, avdd1/avss1 for all other analog circuits like clock oscillator, pll circuits, system clock synthesizer and a/d and d/a converters. the i 2 c interface has an own supply region via pin i2cvdd. connecting this to the microcontroller supply assures that the i 2 c bus always works as long as the microcontroller is alive so that the operating modes can be selected. beside these regions, the dc/dc converters have start-up circuits of their own which get their power via pin vsensx. 2.6.2. dc/dc converters the mas 35x9f has two embedded high-performance step-up dc/dc converters with synchronous rectifiers to supply both the dsp core itself and external circuitry such as a controller or flash memory at two different voltage levels. an overview is given in fig. 2?7 on page 13. the dc/dc converters are designed to generate an output voltage between 2.0 v and 3.5 v which can be programmed separately for each converter via the i 2 c interface (see table 3.3). both converters are of boot- strapped type allowing to start up from a voltage down to 0.9 v for use with a single battery or nicd/nimh cell. the default output voltages are 3.0 v. both converters are enabled with a high level at pin dcen and enabled/disabled by the i 2 c interface. the mas 35x9f dc/dc converters feature a constant- frequency, low noise pulse width modulation (pwm) mode and a low quiescent current, pulse frequency modulation (pfm) mode for improved efficiencies at low current loads. both modes ? pwm or pfm ? can be selected independently for each converter via i 2 c interface. the default mode is pwm. in pwm mode the switching frequency of the power- mosfet-switches is derived from the crystal oscilla- tor. switching harmonics generated by constant fre- quency operation are consistent and predictable. when the audio codec is enabled, the switching fre- quency of the converters is synchronised to the audio codec clock to avoid interferences into the audio band. the actual switching frequency can be selected via the i 2 c-interface between 300 khz and 580 khz (for details see dcfr register in table 3?4 on page 25). in the pfm operation mode, the switching frequency is controlled by the converters themselves. it will be just high enough to service the output load, thus resulting in the best possible efficiency at low current loads. the pfm mode does not need a clock signal from the crys- tal oscillator. if both conv erters do not use the pwm- mode, the crystal clock will be shut down as long it is not needed by other internal blocks. the synchronous rectifier bypasses the external schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improve- ment. by default, the p-channel synchronous rectifier switch is turned on when the voltage at pin(s) dcson exceeds the converter?s output voltage at pin(s) vsensn, and is turned off when the induc tor current drops below a threshold. if one or both converters are disabled, the corr esponding p-channel switch will be turned on, connecting the battery voltage to the dc/ dc converters output vo ltage at pin vsensn. how- ever, it is possible to individually disable both synchro- nous rectifier switches by setting the corresponding bits (bit[8] and [0] in dccf-register). if both dc/dc-converters are off, a high signal may be applied at pin dcen. this will start the converters in their default mode (pwm with 3.0 v output voltage). the pup signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output voltages have dropped 200 mv below their pro- grammed output voltage. the signal at pin pup can be used to control the reset of an external microcontroller (see section 2.11.2. on page 18 for details on the start- up procedure). if only dc/dc-converter 1 is used, the output of the unused converter 2 (vsens2) must be connected to the output of converter 1 (vsens1) to make the pup signal work properly. also, if a dc/dc-converter is not used (no inductor connected), the pin dcso must be left vacant. data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 13 2.6.3. power supply configurations one of the following supply configurations may be used: ? power-optimized solution (recommended opera- tion). dc/dc 1 (e.g. 2.2 v) drives the mas 35x9f dsp and the audio circuitry, dc/dc 2 (e.g. 2.7 v) supplies controller and flash (see fig. 2?8 on page 14) ? volume-optimized solution. dc/dc 1 (e.g. 2.7 v) supplies controller, flash and mas 35x9f audio parts, dc/dc 2 generates e.g. 2.2 v for the mas 35x9f dsp (see fig. 2?9 on page 14). ? minimized external components. dc/dc 1 operates on, e.g., 2.7 v and feeds all components, dc/dc 2 remains off (see fig. 2?10 on page 14). ? external power supply. all components are powered by an external source, no dc/dc converter is used (see fig. 2?11 on page 14). if dc/dc converter 1 is used, it must supply the analog circuits (pins avdd0, avdd1) of the mas 35x9f. if only one dc/dc converter is required, dc/dc1 must be used. pin dcso2 must be left vacant, pin vsens2 should be connected to pin vsens1. if the dc/dc converters are not used, pin dcen must be connected to vss, dcsox must be left vacant. fig. 2?7: dc/dc converter overview. the dcen input must be c onnected to pin i2cvdd via start-up push button. 15 8 ? + ? + ? + mas 35x9f data sheet 14 june 30, 2004; 6251-505-1ds micronas fig. 2?8: solution 1: power-optimized fig. 2?9: solution 2: volume-optimized fig. 2?10: solution 3: minimized components fig. 2?11: solution 4: external power supply vsens1 avdd0/1 vsens2 xvdd vdd i 2 cvdd e.g. 2.2 v e.g. 2.7 v on on dsp dc/dc 1 i 2 c dc/dc 2 analog parts flash data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 15 2.7. mp3 block input mode a new so-called mp3 block input mode is now avail- able which improves the input timing behavior of the mas 35x9f mpeg 1/2/2.5 layer 3 decoder. the fol- lowing sections provide a detailed description of this new mode. 2.7.1. functional description of the mp3 block input mode in mp3 block input, the mas 35x9f generates a demand for new input data each time one of its two input buffers becomes available. the controller then has to send one block of input data via the serial inter- face sdib. the block size is 2048 byte. the demand is signalized via a pulse on the eod pin. fig. 2?12 shows that the number of interrupts per sec- ond does not depend on the data rate at the serial interface. the maximum input data bit clock rate sup- ported by the mas 35x9f for all mpeg audio sampling rates is 1.4 mhz. table 2?2 shows the average number of interrupts per second for several typical mp3 bit rates. the time period between two interrupts may vary slightly even for fixed bit rate input streams due to the mp3 specific bit reservoir. fig. 2?12: data block timing diagram table 2?2: mp3 bit rate vs. number of interrupts bit rate [kbit/s] number of interrupts [1/s] 320 20 256 16 224 14 192 12 160 10 128 8 112 7 96 6 80 5 64 4 interrupt a) b) data blocks in a) and b) contain the same number of bytes. data block a) is sent with a lower data rate than data block b). t sic sic interrupt mas 35x9f data sheet 16 june 30, 2004; 6251-505-1ds micronas 2.7.2. setup table 3?3 on page 24 lists the new bits, uic cells, and registers to setup the mp3 block input mode. 2.7.2.1. resync timeout in case the mp3 decoder loses the synchronization (e.g. due to corrupted input data), the output is softly muted and a resync loop is entered where the mas 35x9f can be accessed via i 2 c. the loop is left and the re-synchronization procedure continues in any of the following cases: ? the last input data block is fully sent, ? the validate bit of iocontrolmain is set (d0:346, bit[0]), ? the timeout is reached (resynctimeout in table 3?3),the end bit is set (this bit will be reset by the mas 35x9f). 2.7.2.2. detailed setup after the mpeg audio decoder application has been selected, the following settings enable the mp3 block decoding process. play mp3 1. write 0x318 into serialinconfig. 2. write iocontrolmain with bit[2] and bit[0] equal one. 3. write iocontrolmain with bit[2] equals zero and bit[0] equals one. 4. write 0x0 into resynctimeout. 5. write 0x0 into softmute. 6. enable eodq interrupt for sending data in controller. 7. set startbit in mp3blockconfig. 8. send data block of 2048 byte when eodq goes high. stop/pause mp3 1. write 0x1 into softmute. 2. clear start bit in mp3blockconfig. 2.8. battery voltage supervision independent of the dc/dc converters, a battery volt- age supervision circuit (at pin vbat) is provided. it can be programmed to supervise one or two battery cells. the voltage is measured by subsequently setting a series of voltage thresholds and checking the respec- tive comparison result in register 77 hex . 2.9. interfaces the mas 35x9f uses an i 2 c control interface, a serial input interface for mpeg bit streams, and digital audio output interfaces for the decoded audio data (i 2 s and s/pdif). s/pdif input is available after software download. a parallel i/o interface (pio) may be used for fast data exchange. 2.9.1. i 2 c control interface for controlling and program download purposes, a standard i 2 c slave interface is implemented. a detailed description of all functions can be found in section 3. 2.9.2. s/pdif input interface the s/pdif interface receives a one-wire serial bus signal. in addition to the signal input pin spdi1/spdi2, a reference pin spdir is provided to support balanced signal sources or twisted pair transmission lines. the synchronization time on the input signal is <50ms. s/pdif input is not supported for mpeg 1/2 layer 2/3 and mpeg 2 aac. micronas has developed a download software for flexi- ble usage of the s/pdif i/o and sdi/sdo interfaces. it is described in download software supplement i2spdif (6251-505-1pds). 2.9.3. s/pdif output the s/pdif output of the baseband audio signals is implemented at pin spdo since version b4. the channel status bits can be set as described in table 3?9. data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 17 2.9.4. multiline serial audio input (sdi, sdib) there are two multiline serial audio input interfaces (sdi, sdib) each consisting of the three pins si(b)c, si(b)i, and si(b)d. the standard firmware only sup- ports sdib for bit-stream signals, while pcm-inputs should be routed to sdi. the interfaces can be configured as continuous bit- stream or word-oriented inputs. for the mpeg bit streams, the word strobe pin sibi must always be con- nected to v ss ; bits must be sent msb first as created by the encoder. if the download software (refer to download software supplement i2spdif (6251-505-1pds)) is used, the interface acts as an i 2 s-type with si(b)i as a word- strobe for pcm data. for the demand mode (see section 2.5.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). pin eod is used to interrupt the data flow whenever the input buffer of the mas 35x9f is filled. for controlling details, please refer to table 3?9 on page 33. 2.9.5. multiline serial output (sdo) the serial audio output interface of the mas 35x9f is a standard i 2 s-like interface consisting of the data lines sod, the word strobe soi and the clock signal soc. it is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted soi signal). if the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. the 12 trailing bits are set to zero by default. 2.9.6. parallel input/output interface (pio) the parallel interface of the mas 35x9f consists of the 8 data lines pi12...pi19 (msb) and the control lines pcs , pr, prtr , prtw , and eod . it can be used for data exchange with an external memory, for fast pro- gram download and for other special purposes as defined by the dsp software. for mpeg data input, the pio interface is activated by setting bits[9] and [8] in d0:346 to 01. for the hand- shake protocol, please refer to section 4.6.2.8. on page 78. 2.10. mpeg synchronization output the signal at pin sync is set to ?1? after the internal decoding for the mpeg header has been finished for one frame. the rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control info rmation and ancillary data. as soon as the mas 35x9f has received the sync reset command (see section 4.6.2.6. on page 75), the sync signal is cleared. if the controller does not issue a reset command, the sync signal returns to ?0? as soon as the decoding of the next mpeg frame is started. mpeg status an d ancillary data become invalid until the frame is completely decoded and the signal at pin sync rises again. the controller must have finished reading all mpeg information before it becomes invalid. the mpeg layer 2/3 frame lengths are given in table 2?3. aac has no fixed frame length. fig. 2?13: schematic timing of the signal at pin sync. the signal is cleared at t read when the controller has issued a clear sync signal command (see section 4.6.2.6. on page 75). if no command is issued, the signal returns to ?0? just before the decoding of the next mpeg frame. table 2?3: frame length in mpeg layer 2/3 f s /khz frame length layer 2 frame length layer 3 48 24 ms 24 ms 44.1 26.12 ms 26.12 ms 32 36 ms 36 ms 24 24 ms 24 ms 22.05 26.12 ms 26.12 ms 16 36 ms 36 ms 12 not available 48 ms 11.025 not available 52.24 ms 8 not available 72 ms v h v l t read t frame = 24...72 ms mas 35x9f data sheet 18 june 30, 2004; 6251-505-1ds micronas 2.11.default operation this sections refers to the standard operation mode ?power-optimized solution? (see section 2.6.3.). 2.11.1. stand-by functions after applying the battery voltage, the system will remain stand-by, as long as the dcen pin level is kept low. due to the low stand-by current of cmos circuits, the battery may remain connected to dcson/vsensn at all times. 2.11.2. power-up of the dc/dc converters and reset the battery voltage must be applied to pin dcson via the 22 h inductor and, furthermore, to the sense pin vsensn via a schottky diode (see fig. 2?7 on page 13). for start-up, the pin dcen must be connected via an external ?start? push button to the i2cvdd supply, which is equivalent to the battery supply voltage (> 0.9 v) at start-up. the supply at dcen must be applied until the dc/dc converters have started up (signal at pin pup) and then removed for normal operation. as soon as the output voltage at vsensn reaches the default voltage monitor reset level of 3.0 v, the respec- tive internal pupn bit will be set. when both pupn bits are set, the signal at pin pup will go high and can be used to start and reset the microcontroller. before transmitting any i 2 c commands, the controller must issue a power-on reset to pin por . the separate supply pin i2cvdd ensures that the i 2 c interface works independently from the dsp or the audio codec. now the desired supply voltage can be programmed at i 2 c subaddress 76 hex . data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 19 2.11.2.1. important advice for turn-on and operat- ing voltage before the 2.2 v are programmed at the dcdc con- verter, dsp+codec must be enabled. operating and turn-off is possible down to 2.2 v. the sequence should be similar to the following: 1. start dcdc 2. set dcdc to 2.5 v turn on dsp+codec write app-select memory cell read app-running mem cell if okay: set dcdc to 2.2 v set other mem cells set other codec registers ..... 3. demute...send data 4. mute...stop data.....loop "3)" "4)"... 5. turn off dsp+codec goto "2)" etc..... the signal at pin pup will retu rn to low only when both pupn flags (i 2 c subaddress 76 hex ) have returned to zero. care must be taken when changing both dc/dc output voltages to higher values. in this case, both out- put voltages are momentarily insufficient to keep the pupn flags up; the resulting dip in the signal at the pup pin may, in turn, reset the microcontroller. to avoid this condition, only one dc/dc output voltage should be changed at a time. before modifying the second voltage, the microcontroller must wait for the pupn flag of the first voltage to be set again. if only dc/dc converter 1 is used, the reference volt- age of the second, unused converter should be set to a lower value than that of converter 1, and its pin vsens2 should be connected to vdd. the operating mode pulse width modulation, or pulse frequency modulation, are controlled at i 2 c subad- dress 76 hex , the operating frequency at i 2 c subad- dress 77 hex . mas 35x9f data sheet 20 june 30, 2004; 6251-505-1ds micronas 2.11.3. reset signal specification after power-up, a reset signal should be applied to the pin por by the microcontroller as follows: fig. 2?14: reset signal at pin por note: the slew rate of por should be as high as pos- sible, but must be glitch-free in any case . slew rate typ.: 1 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 21 2.11.4.control of the signal processing before starting the dsp, the controller should check for a sufficient voltage supply (respective flag pupn at i 2 c subaddress 76 hex ). the dsp is enabled by setting the appropriate bit in the control register (i 2 c subad- dress 6a hex ). the nominal frequency of the crystal oscillator must be written in to d0:348. afte r an initial- ization phase of 5 ms, the dsp data registers can be accessed via i 2 c. input and output control is performed via memory loca- tion d0:346 and d0:347. the serial input interface sdib is the default. the decoded audio can be routed to either the s/pdif, the sdo and the analog outputs. the output clock signal at pin clko is defined in d0:349. all changes in the d0 memory cells become effective synchronously upon setting the lsb of main i/o con- trol (see table 3?9 on page 33). therefore, this cell should always be written last. the digital volume control (see table 3?9 on page 33) is applied to the output signal of the dsp. the decoded audio data will be available at the spdo out- put interface in the next version. the dsp does not have to be started if its functions are not required, e.g., for routing audio through the codec part of the ic via the a/d and the d/a convert- ers. 2.11.5.start-up of the audio codec before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag pupn at i 2 c subaddress 76 hex ). the audio codec is enabled by setting the appropriate bit at the control register (i 2 c subaddress 6a hex ). after an initialization phase of 5 ms, the dsp data registers can be accessed via i 2 c. the a/d and the d/a con- verters must be switched on explicitly (register 00 00 hex at i 2 c subaddress 6c hex ). the d/a convert- ers may either accept data from the a/d converters or the output of the dsp, or a mix of both 1) (register 00 06 hex and 00 07 hex at i 2 c subaddress 6c hex ). finally, an appropriate output volume (register 00 10 hex at i 2 c subaddress 6c hex ) must be selected. 2.11.6.power-down all analog outputs should be muted and the a/d and the d/a converters must be switched off (register 00 10 hex and 00 00 hex at i 2 c subaddress 6c hex ). the dsp and the audio codec must be disabled (clear dsp_en and codec_en bits in the control register, i 2 c subaddress 6a hex ). by clearing both dc/dc enable flags in the control register (i 2 c subaddress 6a hex ), the microcontroller can power down the com- plete system. 1) mixer available in version a2 and later; in version a1, please use selector 00 0f hex . mas 35x9f data sheet 22 june 30, 2004; 6251-505-1ds micronas 3. controlling 3.1. i 2 c interface controlling between the mas 35x9f and the external controller is done via an i 2 c slave interface. 3.1.1. device address the device addresses are 3c/3e hex (device write ?dw?) and 3d/3f hex (device read, ?dr?) as shown in table 3?1. the device address pair 3c/3d hex applies if the dvs pin is connected to vss, the device address pair 3e/3f hex applies if the dvs pin is connected to i2cvdd. i 2 c clock synchronization is used to slow down the interface if required. 3.1.2. i 2 c registers and subaddresses the interface uses one level of subaddresses. the mas 35x9f interface has 7 subaddresses allocated for the corresponding i 2 c registers. the registers can be divided into three categories as shown in table 3? 2. the address 6a hex is used for basic control, i.e. reset and task select. the other addresses are used for data transfer from/to the mas 35x9f. the i 2 c registers of the mas 35x9f are 16 bits wide, the msb is denoted as bit[15]. transmissions via i 2 c bus have to take place in 16-bit words (two byte trans- fers, msb sent first); thus, for each register access, two 8-bit data words must be sent/received via i 2 c bus. 3.1.3. naming convention the description of the various controller commands uses the following formalism: ? abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don?t care ? memory addresses, like d1:89f, are always in hexa- decimal notation. ? a data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. ? data values in nibbles are always shown in hexa- decimal notation. ? a hexadecimal 20-bit number d is written, e.g. as d = 17c63 hex , its five nibbles are d0 = 3 hex , d1 = 6 hex , d2 = c hex , d3 = 7 hex , and d4 = 1 hex . ? variables used in the following descriptions: i2c address: dw3c/3e hex i 2 c device write dr3d/3f hex i 2 c device read dsp core: data_write68 hex dsp data write data_read69 hex dsp data read codec: codec_write6c hex codec write codec_read6d hex codec read ? bus signals sstart pstop a ack = acknowledge n nak = not acknowledge wwait = i 2 c clock line is held low while the mas 35x9f is processing the current i 2 c command ? symbols in the telegram examples < start condition > stop dd data bytes xx ignore all telegram numbers are hexadecimal, data origi- nating from the mas 35x9f are represented as gray letters. example: data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 23 3.2.1. write direct configuration registers the write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit data word. 3.2.2. read direct configuration register to check the pup1 and pup2 power-up flags, it is necessary to read back the content of the direct config- uration registers. fig. 3?1: example of an i 2 c bus protocol for the mas 35x9f (msb first; data must be stable while clock is high) table 3?2: i 2 c subaddresses sub- address (hex) i 2 c- register name function direct configuration 6a control controller writes to mas 35x9f control register 76 dccf controller writes to first dc/dc configuration reg- ister 77 dcfr controller writes to second dc/dc configura- tion register dsp core access 68 data_write controller writes to mas 35x9f dsp 69 data_read controller reads from mas 35x9f dsp codec access 6c codec_write controller writes to mas 35x9f codec regis- ter 6d codec_read controller reads from mas 35x9f codec regis- ter sdw subaddr. wa p d3,d2 d1,d0 a a a sdw subaddr. s dr p d3,d2 a n wa a wa d1,d0 high byte data low byte data ap example: i2c write access sda scl 1 0 s p dr example: i 2 c read access dw subaddress s dw subaddress high byte data low byte data p n w = wait a = acknowledge (ack) n = not acknowledge (nak) s = start p = stop s s a w a w a a a w a a w w mas 35x9f data sheet 24 june 30, 2004; 6251-505-1ds micronas table 3?3: l3 block input mode user interface (all addresses in hex notation) addr. name description d0:346 iocontrolmain bit[1 5] mp3 block input select 0: mp3 block input mode off 1: mp3 block input mode on works for input at serial input interface b (bit[9:8] of iocontrolmain = 00 bin ) reset value is 0x8024 (see table 3?2). r0:68 mp3blockconfig bit[17] data end bit disables resync timeout. should be set by the controller at the end of an input file (file end, stop, or pause) when the last requested data block has been fully sent. 0: resync timeout enabled 1: resync timeout disable ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 25 table 3?4: direct configuration registers i 2 c sub- address (hex) function name 6a control register (reset value = 3000 hex ) bit[15:14] analog supply voltage range code agndc recommended for voltage range of avdd 00 1.1 v 2.0 ... 2.4 v (reset) 01 1.3 v 2.4 ... 3.0 v 10 1.6 v 3.0 ... 3.6 v 11 reserved reserved higher voltage ranges permit higher output levels and thus a better signal-to- noise ratio. bit[13] enable dc/dc 2 (reset=1) bit[12] enable dc/dc 1 (reset=1) both dc/dc converters ar e switched on by default with dcen = high (1). bit[11] enable and reset audio codec 2) bit[10] enable and reset dsp core 2) for normal operation (mpeg-decoding and d/a conversion), both, the dsp core and the audio codec have to be enabled after the power-up procedure. the dsp can be left off if an audio signal is routed from the analog inputs to the analog outputs (set bit[15] in codec register 00 0f hex ). the audio codec can be left off if the dsp uses digital inputs and outputs only. bit[9] reset codec bit[8] reset dsp core bit[7] enable crystal input clock divider of 1.5 (extended range up to 28 mhz) 1) bit[6:0] reserved, must be set to zero control 1) refer to section 4.6.3. on page 79 2) refer to section 2.11.2.1. mas 35x9f data sheet 26 june 30, 2004; 6251-505-1ds micronas 76 dccf register (reset = 5050 hex ) dccf dc/dc converter 2 bit[15] pup2: voltage monitor 2 flag (readback) bit[14:11] converter 2 output voltage with respect to vref 2) code nominal set level reset level output volt. of pup2 of pup2 1111 3.5 v 3.4 v 3.3 v 1110 3.4 v 3.3 v 3.2 v 1101 3.3 v 3.2 v 3.1 v 1100 3.2 v 3.1 v 3.0 v 1011 3.1 v 3.0 v 2.9 v 1010 3.0 v 2.9 v 2.8 v (reset) 1001 2.9 v 2.8 v 2.7 v 1000 2.8 v 2.7 v 2.6 v 0111 2.7 v 2.6 v 2.5 v 0110 2.6 v 2.5 v 2.4 v 0101 2.5 v 2.4 v 2.3 v 0100 1) 2.4 v 2.3 v 2.2 v 0011 1) 2.3 v 2.2 v 2.1 v 0010 1) 2.2 v 2.1 v 2.0 v bit[10] mode 1 pulse frequency modulation (pfm) 0 pulse width modulation (pwm) (reset) bit[9:8] reserved, must be set to zero the dc/dc converters are up-converters only. thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. dc/dc converter 1 bit[7] pup1: voltage monitor 1 flag (readback) bit[6:3] converter 1 output voltag e at vsens1 with respect to vref (see bits 14 to 11) 2) bit[2] mode 1 pulse frequency modulation (pfm) 0 pulse width modulation (pwm) (reset) bit[1:0] reserved, must be set to zero note, that the reference voltage for dc/dc converter 1 is derived from the main reference source supplied via pin avdd1. therefore, if this dc/dc con- verter is used, its output must be connected to the analog supply. the dc/dc converters are up-converters only. thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) refer to section 4.3.3. on page 59 2) refer to section 2.11.2.1. table 3?4: direct configuration registers, continued i 2 c sub- address (hex) function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 27 77 dcfr register (reset = 00 hex ) dcfr battery voltage monitor bit[15] comparison result (readback) 1 input voltage at pin vbat above defined threshold 0 input voltage at pin vbat below defined threshold bit[14] number of battery cells 0 1 cell (range 0.8...1.5 v) (reset) 1 2 cells (range 1.6...3.0 v) bit[13:10] voltage threshold level 1 cell 2 cells 1111 1.5 3.0 v 1110 1.45 2.9 v ... 0010 0.85 1.7 v 0001 0.8 1.6 v 0000 battery voltage supervision off (reset) bit[9:8] reserved, must be set to 0 the result is stable 1 ms after enabling. the setup time for switching between two thresholds is negligibly small. for power management reasons, the battery voltage monitor should be switched off by setting bit[13:10] to zero when the measurement is completed. dc/dc converter frequency control (pwm) bit[7:4] reserved, must be set to 0 bit[3:0] frequency of dc/dc converter reference: 24.576 22.5792 18.432 mhz 0111 315.1 289.5 297.3 khz 0110 323.4 297.1 307.2 khz 0101 332.1 305.1 317.8 khz 0100 341.3 313.6 329.1 khz 0011 351.1 322.6 341.3 khz 0010 361.4 332.0 354.5 khz 0001 372.4 342.1 368.6 khz 0000 384.0 352.8 384.0 khz (reset) 1111 396.4 364.2 400.7 khz 1110 409.6 376.3 418.9 khz 1101 423.7 389.3 438.9 khz 1100 438.9 403.2 460.8 khz 1011 455.1 418.1 485.1 khz 1010 472.6 434.2 512.0 khz 1001 491.5 451.6 542.1 khz 1000 512.0 470.4 576.0 khz if the audio codec is not enabled (bit[11] of the control register at i 2 c-sub- address 6a hex is zero), the clock for the dc/dc converters is directly derived from the crystal frequency (nominal 18.432 mhz). otherwise, the synthesizer clock is used as the reference (please refer to the respective column in table 2?1 on page 11). table 3?4: direct configuration registers, continued i 2 c sub- address (hex) function name mas 35x9f data sheet 28 june 30, 2004; 6251-505-1ds micronas 3.3. dsp core 3.3.1. access protocol the i 2 c data register is used to communicate with the internal firmware of the mas 35x9f. it is readable (subaddress ?data_read?) and writable (subaddress ?data_write?) and also has a length of 16 bits. the data transfer is done with the most significant bit (m) first. a special command language is used that allows the controller to access the dsp registers and ram cells and thus monitor internal states, set the parameters for the dsp firmware, control the hardware, and even pro- vide a download of alternative software modules. the dsp commands consist of a ?code? which is sent to the i 2 c data register together with additional parame- ters. fig. 3?2: general core access protocol table 3?6 gives an overview over the different com- mands which the dsp core receives via the i 2 c data register. the ?code? is always the first data nibble transmitted after the ?data_write? subaddress byte. a second auxiliary code nibble is used for the short memory (16-bit) access commands. the mas 35x9f firmware scans the i 2 c interface peri- odically and checks for pending or new commands. the commands are then executed by the dsp during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. however, due to some time critical firmware parts, a certain latency time for the response has to be expected at the locations marked with a ?w? (= wait). the theoretical worst case response time does not exceed 4 ms. however, the typical response time is less than 0.5 ms. due to the 16-bit width of the i 2 c data register, all actions transmit telegrams with multiples of 16 data bits. table 3?5: data register bit assignment 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ml ... sdw data_write code ,... ...,... wa a a a table 3?6: basic controller command codes code (hex) command function 0...3 run start execution of an internal program. run with start address 0 means freeze the operating system. 5 read ancillary data the controller reads a bloc k of mpeg ancillary data from the mas 35x9f 6 fast program download the controller downloads custom software via the pio interface 7 read ic version the controller reads the version information of the ic a read from register the controller reads an internal register of the mas 35x9f b write to register the controller writes an internal register of the mas 35x9f c read d0 memory the controller reads a block of the dsp memory d read d1 memory the controller reads a block of the dsp memory e write d0 memory the controller wr ites a block of the dsp memory f write d1 memory the controller wr ites a block of the dsp memory data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 29 3.3.2. data formats the internal data word size is 20 bits. all ram- addresses can be accessed in a 20-bit mode via i 2 c bus. because of the 16-bit width of the i 2 c data regis- ter the full transfer of all 20 bits requires two 16-bit i 2 c words. some commands only access the lower 16 bits of a cell. for fast access of internal dsp states the processor core also has an address space of 256 data registers. the internal data format is a 20 bit two?s complement denoted ?r?. if in some cases a fixed point notation ?v? is necessary. the conversion between the two forms of notation is done as follows: r = v*524288.0+0.5; ( ? ? 3.3.2.1. run and freeze (codes 0 hex to 3 hex ) the run command causes the start of a program part at address a = (a3,a2,a1,a0). since nibble a3 is also the command code (see table 3?6), it is restricted to values between 0 and 3. this command is used to start alternate code or downloaded code from a ram- area that has been configured as program ram. if the start address is 1000 hex a < 3fff hex and the respective ram area has been configured as program ram (see table 3?8 on page 32), the mas 35x9f continues execution with a custom program already downloaded to this area. example 1: start program execution at address 345 hex : mas 35x9f data sheet 30 june 30, 2004; 6251-505-1ds micronas 3.3.2.4. read memory (codes c hex and d hex ) the mas 35x9f has 2 memory areas of 2048 words denoted d0 and d1. the memory areas d0 and d1 can be written by using the codes c hex and d hex , respectively. the read d0 memory command gives the controller access to all 20 bits of the d0/d1 memory cells. the telegram to read 3 words starting at location d1:100 is data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 31 3.3.2.9. default read the default read command is the fastest way to get information from the mas 35x9f. executing the default read in a polling loop can be used to detect a special state during decoding. the default read command immediately returns the lower 16 bit content of a specific ram location as defined by the pointer d0:ffb. the pointer must be loaded before the first default read action occurs. if the msb of the pointer is set, it points to a memory location in d1 rather than to one in d0. example: for watching d1:123 the pointer d0:ffb must be loaded with 8123 hex : mas 35x9f data sheet 32 june 30, 2004; 6251-505-1ds micronas 3.3.2.12.read ic version (code 7 hex ) with this command the version of the ic is read in two 16 bit words. the first word n = n3,n2,n1,n0 contains the ic?s major number (one nibble for each digit). the second word ( d = d3,d2,d1,d0) returns the version as shown in table 3?7. example: read the version information for mas 35x9f, derivate 0, order version b2: data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 33 3.3.4.1. application selection and application running the appselect cell is a global user interface configura- tion cell, which has to be written in order to start a spe- cific application. the apprunning cell is a global user interface status cell, which indicates, which application loop is actually running. 1. write ?0? to appselect 2. check apprunning for ?0? 3. write value to appselect according to table 3?9 (determines start time of application program) 4. apply necessary/want ed control settings (d0:346..357) 3.3.4.2. application specific control the configuration of the mpeg layer 2/3, aac decod- ing and the g.729 codec firmware is done via the con- trol memory cells described in table 3?10. the changes applied to any of the control memory cells have to be validated by setting bit[0] of memory cell main i/o control. this bi t will be reset automatically after the changes have been taken over by the dsp. the status memory cells in table 3?11 are used to read the decoder status and to get additional mpeg bitstream information. note: dsp memory cells not given in table 3?9 or table 3?10 must not be written. table 3?9: d0 control memory ce lls: mode selection memory address (hex) function name d0:34b application selection all appselect is used for selecting an application. this is done by setting the appropriate bit to one. it is principally allowed to set more than one bit to one, e.g. setting appselect to 1c hex will select all mpeg audio decoders. the auto-detection featur e will automatically detect the layer 2, layer 3, or aac data. setting bit[0] or bit[1] will make th e dsp loop in the os loop or the top level loop respectively. to add/remove mpeg layers while running in mpeg decoding mode (e.g. change from layer 2, layer 3 (0c hex ) to layer 2, layer 3, aac (1c hex )), the application selection has to be reset to 00 hex before writing the new value. bit[5] g.729 codec bit[4] mpeg aac decoder bit[3] mpeg layer 3 decoder bit[2] mpeg layer 2 decoder bit[1] top level bit[0] operating system appselect d0:34c application running all the apprunning cell is a global user inte rface status cell, that indicates which application loop is actually running. prior to writin g any of the configuration registers or memory cells (except appselect), it has to be checked whether the appropriate bit(s) in the apprunning cell is set. bit[5] g.729 codec bit[4] mpeg aac decoder bit[3] mpeg layer 3 decoder bit[2] mpeg layer 2 decoder bit[1] top level bit[0] operating system apprunning mas 35x9f data sheet 34 june 30, 2004; 6251-505-1ds micronas table 3?10: d0 control memory cells memory address (hex) function name d0:346 main i/o control (reset = 8025 hex ) mpeg iocontrolmain is used for selecting/de selecting the appropriate data input interface and for setting up the serial data output interface. in serial input mode the coded audio data (layer 2, layer 3, aac) is expected at the serial input interface sdib (default). in the 8-bit-parallel input mode the pio pins pi[19:12] are used. bit[15] mp3 block input selection 0: mp3 block input mode off 1: mp3 block input mode on bit[14] invert serial output clock (soc) 0 (reset) do not invert soc 1invert soc bit[13:12] reserved, must be set to zero bit[11] serial data output delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe bit[10] reserved, must be set to zero bit[9:8] input select main 00 (reset) serial input at interface b 01 parallel input at pio pins pi[19...12] 10 reserved for future use 11 reserved for future use bit[7:6] reserved, must be set to zero bit[5] sdo word strobe invert 0 do not invert 1 (reset) invert outgoing word strobe signal bit[4] bits per sample at sdo 0 (reset) 32 bits/sample 1 16 bits/sample bit[3] reserved, must be set to zero bit[2] serial data input interface b clock invert (pin sibc) 0 not inverted (data latched at rising clock edge) 1 (reset) incoming clock signal is inverted (data latched at falling clock edge) bit[1] 0 (reset) demand mode (pll off, mas 35x9f is clock master) 1 broadcast mode (pll on, clock of mas 35x9f locks on data stream) bit[0] validate no forced evaluation of control memory cells 0 (reset) 1 changes in control memory will become effective bit[0] is reset after the dsp has recognized the changes. the controller should set this bit after the other d0 co ntrol memory cells have been initialized with the desired values. iocontrolmain data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 35 d0:347 interface status control (reset = 05 hex ) mpeg this control cell allows to enable/disable the data i/o interfaces. in addition, the clock of the output data interface interfaces, s/pdif and sdo, can be set to a low-impedance mode. bit[6] s/pdif input selection (used for download modules) 0 (reset) select s/pdif input 1 1 select s/pdif input 2 bit[5] enable/disable s/pdif output 0 (reset) enable s/pdif output 1 s/pdif output (invalid) bit[4] reserved, must be set to zero bit[3] enable/disable serial data output sdo 0 (reset) sdo valid data 1 sdo invalid data bit[2] output clock characteristic (sdo and s/pdif outputs) 0 low impedance 1 (reset) high impedance bit[1] reserved, must be set to zero bit[0] enable/disable sdi 1) 0 enable 1 (reset) disable both digital outputs, s/pdif and i 2 s, and the d/a converters may use the decoded audio independent of each other. changes at this memory address must be validated by setting bit[0] of d0:346 hex . interfacecontrol d0:348 oscillator frequency (reset = 18432 dec ) all bit[19:0] oscillator frequency in khz in order to achieve a correct internal operating frequency of the dsp, the nom- inal crystal frequency has to be deposited into this memory cell. changes at this memory address must be validated by setting bit[0] of d0:346 hex . ofreqcontrol 1) note: the pins sic, sii, sid are switched to output mode, if bit [0] = 1 (reset value). table 3?10: d0 control memory cells, continued memory address (hex) function name mas 35x9f data sheet 36 june 30, 2004; 6251-505-1ds micronas d0:349 output clock configuration (affects pin clko) (reset = 80000 hex ) all bit[19] clko configuration 0 output clock signal at clko 1 (reset) clko is tristate the clko output pin of the mas 35x9f can be disabled via bit[19]. bit[18] reserved, must be set to zero bit[17] additional division by 2 if scaler is on (bit[8] cleared) 0 (reset) oversampling factor 512/768 1 oversampling factor 256/384 bit[16:9] reserved, must be set to zero bit[8] output clock scaler 0 (reset) set output clock according to audio sample rate (see table 2?1) 1 output clock fixed at 24.576 or 22.5792 mhz for a list of output frequencies at pin clko please refer to table 2?1. bit[7:0] reserved, must be set to zero changes at this memory address must be validated by setting bit[0] of d0:346. outclkconfig d0:350 soft mute mpeg %0 (reset) mute off %1 mute on softmute d0:351 s/pdif channel status bits category code setting (reset = 8200 hex ) all spdoutbits table 3?10: d0 control memory cells, continued memory address (hex) function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 37 d0:34d operation mode selection (reset = 0 hex ) g.729 the register is used to switch between basic g.729 operation modes. bit[19:7] reserved, set to 0 bit[6] page headers 0 enable 1 disable if the page headers bit is 0, a header frame is transfered before each page of 50 data frames. if the header bit is 1, all the frames are g.729 data frames. please (see section 3.3.8. on page 44). bit[5:4] decoding speed 00 8 khz (normal) 01 6 khz (slow) 10 12 khz (fast) 11 not allowed the recording (encoding) is always done with a sampling rate of 8 khz. during decoding this control can be used to speed up or slow down the playback. bit[3] reserved, set to 0 bit[2] pause encoder/decoder 0 normal operation 1 pause if the pause bit is set, the processing continues until the current page is fin- ished and then en-/decoding is paused. the pause mode lasts until the pause bit is cleared again or the mode is set to 0. bit[1:0] mode 00 idle 01 decode 10 not allowed 11 encode to switch to encoder operation mode, usercontrol has to be set to 3 hex . then 50 frames are encoded and sent via the pio interface. this is repeated until the usercontrol register is changed. if the transmission of headers is enabled, each page of 50 frames is preceeded by a header frame as shown in fig. 3?4 on page 44. to switch to decoder operation mode, usercontrol has to be set to 1 hex . for decoding with slow speed, usercontrol must be 11 hex , for decoding with fast speed it must be 21 hex . then the decoder is requesting several frames via the pio interface to fill its internal buffer. if enough data is available, 50 frames are decoded. this is repeated until the usercontrol register is changed. if the transmission of headers is enabled, a header frame has to be sent before each page of 50 frames (see fig. 3?4 on page 44). to switch off the encoder or decoder, usercontrol has to be set to 0 hex . then the encoding/decoding and sending/receiving of frames continues until the end of the current page and the operation mode is set to stop. usercontrol table 3?10: d0 control memory cells, continued memory address (hex) function name mas 35x9f data sheet 38 june 30, 2004; 6251-505-1ds micronas d0:34e i 2 s audio input/output interface (reset = 60 hex ) g.729 bit[19:15] reserved, set to 0 bit[14] output clock signal 0 standard signal 1 inverted signal bit[13] reserved, set to 0 bit[12] additional delay of input data related to word strobe 0 no delay 1 1 bit delay bit[11] additional delay of output data related to word strobe 0 no delay 1 1 bit delay bit[10:7] reserveded, set to 0 bit[6] input word strobe signal 0 standard signal 1 inverted signal bit[5] output word strobe signal 0 standard signal 1 inverted signal bit[4] wordlength 0 32 bits/sample 1 16 bits/sample this setting affects the wordlength on the sdi and sdo interfaces. bit[3] input clock signal 0 standard signal 1 inverted signal bit[2:0] reserved, set to 0 changes become effective when the codec is started or the mode is changed by writing to the usercontrol memory cell. sdisdoconfig table 3?10: d0 control memory cells, continued memory address (hex) function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 39 d0:34f interface status control (reset = 25 hex ) g.729 this control cell is used to enable /disable interfaces in g.729 mode. bit[6],[4] reserved, must be set to zero bit [5] reserved, must be set to one bit[3] enable/disable serial data output sdo 0 (reset) sdo valid data 1 sdo invalid data bit[2] output clock characteristic (sdo and s/pdif outputs) 0 low impedance 1 (reset) high impedance bit[1] reserved, must be set to zero bit[0] enable/disable sdi 1) 0 enable 1 (reset) disable g729_interfacecont rol d0:352 volume input control: left gain (reset=80000 hex ) g.729 in_l d0:353 volume input control: right gain (reset=0 hex ) g.729 in_r d0:354 volume output control: left left gain (reset=80000 hex ) all out_ll d0:355 volume output control: left right gain (reset=0 hex ) all out_lr d0:356 volume output control: right left gain (reset=0 hex ) all out_rl d0:357 volume control: right right gain (reset=80000 hex ) all out_rr 1) note: the pins sic, sii, sid are switched to output mode, if bit [0] = 1 (reset value). table 3?10: d0 control memory cells, continued memory address (hex) function name mas 35x9f data sheet 40 june 30, 2004; 6251-505-1ds micronas table 3?11: d0 status memory cells memory address function name d0:fcf aac bitrate in bit/s aacbitrate d0:fd0 mpeg frame counter bit[19:0] number of mpeg frames after synchronization the counter will be incremented with ever y new frame that is decoded. with an invalid mpeg bit stream at its input (e.g. an invalid header is detected), the mas 35x9f resets the mpegframecount to ?0?. mpegframecount d0:fd1 mpeg header and status information bit[15] reserved, must be set to zero bit[14:13] mpeg id, bits 12, 11 of the mpeg header 00 mpeg 2.5 01 reserved 10 mpeg 2 11 mpeg 1 not valid in case of aac decoding (bit[12:11] = 00) bit[12:11] bits 14 and 13 of the mpeg header 00 aac 01 layer 3 10 layer 2 11 layer 1 bit[10] crc protection 0 bitstream protected by crc 1 bitstream not protected by crc bit[9:2] reserved bit[1] crc error 0 no crc error 1 crc error bit[0] invalid frame 0 no invalid frame 1 invalid frame this location contains bits 15...11 of the original mpeg header and other sta- tus bits. it will be set each frame direct ly after the header has been decoded from the bit stream. mpegstatus1 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 41 d0:fd2 mpeg header information bit[15:12] mpeg layer 2/3 bitrate mpeg1, l2 mpeg1, l3 mpeg2+2.5, l2/3 0000 free free free 0001 32 32 8 0010 48 40 16 0011 56 48 24 0100 64 56 32 0101 80 64 40 0110 96 80 48 0111 112 96 56 1000 128 112 64 1001 160 128 80 1010 192 160 96 1011 224 192 112 1100 256 224 128 1101 320 256 144 1110 384 320 160 1111 forbidden forbidden forbidden bit[13:10] sampling frequency for mpeg2-aac in hz 0000..0010 reserved 0011 48000 0100 44100 0101 32000 0110 24000 0111 22050 1000 16000 1001 12000 1010 11025 1011 8000 1100..1111 reserved ... mpegstatus2 table 3?11: d0 status memory cells, continued memory address function name mas 35x9f data sheet 42 june 30, 2004; 6251-505-1ds micronas d0:fd2 (continued) mpeg header information, continued bit[11:10] sampling frequencies in hz mpeg1 mpeg2 mpeg2.5 00 44100 22050 11025 01 48000 24000 12000 10 32000 16000 8000 11 reserved reserved reserved bit[9] padding bit bit[8] reserved bit[7:6] mode 00 stereo 01 joint_stereo (intensity stereo / m/s stereo) 10 dual channel 11 single channel bit[5:4] mode extension (applies to joint stereo only) intensity stereo m/s stereo 00 off off 01 on off 10 off on 11 on on bit[3] copyright protect bit 0/1 not copyright protected/copyright protected bit[2] copy/original bit 0/1 bitstream is a copy/b itstream is an original bit[1:0] emphasis, indicates the type of emphasis 00 none 01 50/15 mpeg crc error counter the counter will be increase d by each crc error dete cted in the mpeg bis- stream. it will not be reset when losing the synchronization. crcerrorcount d0:fd4 number of bits in ancillary data number of valid ancillary bits in the current mpeg frame. numberofancillary- bits d0:fd5 ... d0:ff1 ancillary data (see section 3.3.6. on page 43). ancillarydata table 3?11: d0 status memory cells, continued memory address function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 43 3.3.5. ancillary data the memory fields d0:fd5...d0:ff1 contain the ancil- lary data. it is organized in 28 words of 16 bit each. the last ancillary bit of a fr ame is placed at bit 0 in d0:fd5. the position of the first ancillary data bit received can be located via the content of numberofancillarybits because int[(numberofancillarybits-1)/16] + 1 of memory words are used. example: first get the content of ?numberofancillarybits? mas 35x9f data sheet 44 june 30, 2004; 6251-505-1ds micronas 3.3.7. dsp volume control the digital baseband volume matrix is used for control- ling the digital gain as shown in fig. 3?3. this volume control is effective on both, the digital audio output and the data stream to the d/a converters. the values are in 20-bit 2?s complement notation. table 3?14 shows the proposed settings for the 4 vol- ume matrix coefficients for stereo, left and right mono. the gain factors are given in fixed point notation ( ? fig. 3?3: digital volume matrix 3.3.8. explanation of the g.729a data format the codec is working on a page basis where the encoding and decoding is performed in blocks of 50 g.729 frames, whereas each frame consists of 10 bytes in byte-swapped order (see fig. 3?4). there- fore most changes to the usercontrol register become effective when processing of the current page is fin- ished. the pages are optionally preceeded by 10 byte header frames (see table 3?15). switching directly from encoding to decoding mode (or vice versa) is not allowed. instead, the controller has to send a stop request to the mas 35x9f (writing 0 hex to usercontrol) and must keep on sending data in decod- ing mode or receive data in encoding mode until the current page of 50 frames is finished. after this run-out time, the encoding or decoding can be started again. fig. 3?4: schematic timing of the data transmission with preceeding header ? ? ? ? table 3?14: settings for the digital volume matrix memory d0:354 d0:355 d0:356 d0:357 name ll lr rl rr stereo (default) ? ? ? ? ? ? table 3?15: content of page header byte12345678910 value (hex) 64 6d 72 31 64 61 74 61 f4 01 ... ... ... ... ... page header frame 1 frame 2 frame 3 frame 49 frame 49 page header frame 51 frame 52 frame 99 frame 100 page header frame 101 frame 102 10 ms 10 ms byte 2 byte 1 byte 4 byte 3 byte 6 byte 5 byte 8 byte 7 byte 10 byte 9 64 6d 72 31 64 61 74 61 f4 01 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 45 3.4. audio codec access protocol the mas 35x9f has 16-bit wide registers for the con- trol of the audio codec. these registers are accessed via the i 2 c subaddresses codec_write (6c hex ) and codec_read (6d hex ). 3.4.1. write codec register the controller writes the 16-bit value ( d = d3,d2,d1,d0) into the mas 35x9f codec register ( r = r3,r2,r1,r0). a list of registers is given in table 3?16. example: writing the value 1234 hex into the codec reg- ister with the number 00 1b hex : mas 35x9f data sheet 46 june 30, 2004; 6251-505-1ds micronas 3.4.3. codec registers table 3?16: codec control registers on i 2 c subaddress 6c hex register address (hex) function name converter configuration 00 00 audio codec configuration 0 db is related to the d/a full-scale output voltage please refer to (see section 4.6.3. on page 79). bit[15:12] a/d converter left amplifier gain = n*1.5 ? ? ? ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 47 input mode select 00 08 input mode setting bit[15] mono switch 0 stereo input mode 1 left channel is copied into the right channel bit[14:2] reserved, must be set to 0 bit[1:0] deemphasis select 0 deemphasis off 1 deemphasis 50 s 2 deemphasis 75 s adc_in_mode output mode select 00 06 00 07 d/a converter source mixer mix adc scale mix dsp scale bit[15:8] linear scaling factor (hex) 0off 20 50 % ( ? d/a converter output mode bit[15] mono switch 0 stereo through 1 mono matrix applied bit[14] invert right channel 0 through 1 right channel is inverted bit[1:0] reserved, must be set to 0 in order to achieve more output power a single loudspeaker can be connected as a bridge between pins outl and outr. in this mode bit[15] and bit[14] must be set. dac_out_mode table 3?16: codec control registers on i 2 c subaddress 6c hex , continued register address (hex) function name mas 35x9f data sheet 48 june 30, 2004; 6251-505-1ds micronas bassband features 00 14 bass bit[15:8] bass range 60 hex + + + ? ? ? treble bit[15:8] treble range 60 hex + + + ? ? ? table 3?16: codec control registers on i 2 c subaddress 6c hex , continued register address (hex) function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 49 00 1e loudness bit[15:8] loudness gain 44 hex + + + table 3?16: codec control registers on i 2 c subaddress 6c hex , continued register address (hex) function name mas 35x9f data sheet 50 june 30, 2004; 6251-505-1ds micronas micronas bass (mb) 00 22 mb effect strength bit[15:8] 00 hex mb off (default) 7f hex maximum mb the mb effect strength can be adjusted in 1db steps. a value of 40 hex will yield a medium mb effect. mb_str 00 23 mb harmonics bit[15:8] 00 hex no harmonics are added (default) 64 hex 50% fundamentals + 50% harmonics 7f hex 100% harmonics the mb exploits the psychoacoustic phenomenon of the ?missing fundamental by creating harmonics of the frequencies below the center frequency of the bandpass filter (mb_fc). this enables a loudspeaker to display frequencies that are below its cutoff frequency. the variable mb_har describes the ratio of the harmonics towards the original signal. mb_har 00 24 mb center frequency bit[15:8] 2 20 hz 330hz ... 30 300 hz the mb center frequency defines the center frequency of the mb bandpass filter (see fig. 3?5 on page 52). the center frequency should approximately match the cutoff frequency of the loudspeakers. for high end loudspeakers, this frequency is around 50 hz, for low end speakers around 90 hz mb_fc 00 21 mb shape bit[15:8] 5...30 corner frequency in 10-hz steps (range: 50...300 hz) with a second lowpass filter the steepness of the falling edge of the mb band- pass can be increased (see fig. 3?5 on page 52). choosing the corner fre- quency of this filter close to the center frequency of the bandpass filter (mb_fc) results in a narrow mb frequency range. the smaller this range, the harder the bass sounds. the recommended value is around 1.5 mb switch bit[7:2] reserved, must be set to zero bit[1] mb switch 0mb off 1mb on bit [0] reserved,must be set to zero mb_switch table 3?16: codec control registers on i 2 c subaddress 6c hex , continued register address (hex) function name data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 51 volume 00 12 automatic volume correction (avc) loudspeaker channel bit[15:12] 0 hex avc off (and reset internal variables) 8 hex avc on bit[11:8] 8 hex 8 s decay time 4 hex 4 s decay time 2 hex 2 s decay time 1 hex 20 ms decay time (intended for quick adaptation to the average volume level after track or source change) note: to reset the internal variables, the avc should be switched off and then on again during any track or source change. for standard applications, the recommended decay time is 4 s. avc 00 11 balance bit[15:8] balance range 7f hex left ? ? ? ? ? ? volume control bit[15:8] volume table with 1 db step size 7f hex + + + ? ? ? table 3?16: codec control registers on i 2 c subaddress 6c hex , continued register address (hex) function name mas 35x9f data sheet 52 june 30, 2004; 6251-505-1ds micronas 3.4.4. basic mb configuration with the parameters described in table 3?16, the mic- ronas bass system (mb) can be customized to create different bass effects, as well as to fit the mb to various loudspeaker characteristics. the easiest way to find a good set of parameter is by selecting one of the set- tings below, listening to music with strong bass content and adjusting the mb parameters: ? mb_str: increase/decrease the strength of the mb effect ? mb_har: increase/decrease the content of low fre- quency harmonics ? mb_fc: shift the mb effect to lower/higher frequen- cies ? mb_shape: widen/narrow mb frequency range (which results in a softer/harder bass sound), turn on/off the mb fig. 3?5: micronas bass (mb): bass boost in relation to input signal level table 3?17: codec status registers on i 2 c subaddress 6d hex register address (hex) function name input quasi-peak 00 0a a/d converter quasi-peak detector readout left bit[14:0] positive 15-bit value, linear scale 0000 0% 2000 25% ( ? ? a/d converter quasi-peak detector readout right bit[14:0] positive 15-bit value, linear scale 0000 0% 2000 25% ( ? ? output quasi-peak 00 0c audio processing input quasi-peak detector readout left bit[14:0] positive 15-bit value, linear scale dqpeak_l 00 0d audio processing input quasi-peak detector readout right bit[14:0] positive 15-bit value, linear scale dqpeak_r frequency mb_fc signal level amplitude (db) mb_shape table 3?18: suggested mb settings function mb_str (22 hex ) mb_har (23 hex ) mb_fc (24 hex ) mb_shape (21 hex ) mb off xxxx hex xxxx hex xxxx hex xx00 hex low end headphones, medium effect 5000 hex 3000 hex 0600 hex 0902 hex data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 53 4. specifications 4.1. outline dimensions fig. 4?1: plqfp64-1: p lastic l ow q uad f lat p ackage, 64 leads, 10 mas 35x9f data sheet 54 june 30, 2004; 6251-505-1ds micronas fig. 4?2: pmqfp64-2: p lastic m etric q uad f lat p ackage, 64 leads, 10 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 55 fig. 4?3: pqfn64-1: p lastic q uad f lat n on-leaded package, 64 pins, 9 mas 35x9f data sheet 56 june 30, 2004; 6251-505-1ds micronas 4.2. pin connections and short descriptions nc = not connected, leave vacant lv = if not used, leave vacant s.t.b. = shorted to bagndi if not used dvss = if not used, connect to dvss obl = obligatory; connect as described in circuit diagram ahvss = connect to ahvss pin no. pin name type connection short description plqfp 64-1 pmqfp 64-2 pqfn 64-1 (if not used) 1 1 1 agndc obl analog reference voltage 2 2 2 micin in lv input for internal micro- phone amplifier 3 3 3 micbi in lv bias for internal microphone 4 4 4 inl in lv left a/d input 5 5 5 inr in lv right a/d input 6 6 6 te in obl test enable 7 7 7 xti in obl crystal oscillator (ext. clock) input 8 8 8 xto out lv crystal oscillator output 999por in obl power on reset, active low 10 10 10 vss supply obl dsp supply ground 11 11 11 xvss supply obl digital output supply ground 12 12 12 vdd supply obl dsp supply 13 13 13 xvdd supply obl digital output supply 14 14 14 i2cvdd supply obl i 2 c supply 15 15 15 dvs in obl i 2 c device address selector 16 16 16 vsens1 in/out vdd sense input and power out- put of dc/dc 1 converter 17 17 17 dcso1 supply lv dc/dc 1 switch output 18 18 18 dcsg1 supply vss dc/dc 1 switch ground 19 19 19 dcsg2 supply vss dc/dc 2 switch ground 20 20 20 dcso2 supply lv dc/dc 2 switch output 21 21 21 vsens2 in/out vdd sense input and power out- put of dc/dc 2 converter 22 22 22 dcen in vss dc/dc enable (both con- verters) data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 57 23 23 23 clko out lv clock output 24 24 24 i2cc in/out obl i 2 c clock 25 25 25 i2cd in/out obl i 2 c data 26 26 26 sync out lv sync output 27 27 27 vbat in lv battery voltage monitor input 28 28 28 pup out lv dc converters power-up signal 29 29 29 eod out lv pio end of dma, active low 30 30 30 prtr out lv pio ready to read, active low 31 31 31 prtw out lv pio ready to write, active low 32 32 32 pr in vdd pio dma request, active high 33 33 33 pcs in vss pio chip select, active low 34 34 34 pi19 in/out lv pio data bit[7] (msb) 35 35 35 pi18 in/out lv pio data bit[6] 36 36 36 pi17 in/out lv pio data bit[5] 37 37 37 pi16 in/out lv pio data bit[4] 38 38 38 pi15 in/out lv pio data bit[3] 39 39 39 pi14 in/out lv pio data bit[2] 40 40 40 pi13 in/out lv pio data bit[1] 41 41 41 pi12 in/out lv pio data bit[0] (lsb) 42 42 42 sod out lv serial output data 43 43 43 soi out lv serial output word identifi- cation 44 44 44 soc out lv serial output clock 45 45 45 sid in/out obl serial input data, interface a 46 46 46 sii in/out obl serial input word identifica- tion, interface a 47 47 47 sic in/out obl serial input clock, interface a 48 48 48 spdo out lv s/pdif output interface 49 49 49 sibd in vss serial input data, interface b pin no. pin name type connection short description plqfp 64-1 pmqfp 64-2 pqfn 64-1 (if not used) mas 35x9f data sheet 58 june 30, 2004; 6251-505-1ds micronas 50 50 50 sibc in vss serial input clock, interface b 51 51 51 sibi in vss serial input word identifica- tion, interface b 52 52 52 spdi2 in lv active differential s/pdif input 2 53 53 53 spdi1 in lv active differential s/pdif input 1 54 54 54 spdir in lv reference differential s/ pdif input 1 and 2 55 55 55 filtl in obl feedback input for left amplifier 56 56 56 avdd0 supply obl analog supply for output amplifiers 57 57 57 outl out lv left analog output 58 58 58 outr out lv right analog output 59 59 59 avss0 supply obl anal og ground for output amplifiers 60 60 60 filtr in obl feedback for right output amplifier 61 61 61 avss1 supply obl analog ground 62 62 62 vref obl analog reference ground 63 63 63 pvdd supply obl internal power supply 64 64 64 avdd1 supply obl analog supply pin no. pin name type connection short description plqfp 64-1 pmqfp 64-2 pqfn 64-1 (if not used) data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 59 4.3. pin descriptions 4.3.1. power supply pins the use of all power supply pins is mandatory to achieve correct function of the mas 35x9f. vdd, vss supply digital supply pins. xvdd, xvss supply supply for digital output pins. i2cvdd supply supply for i 2 c interface circuitry. this net uses vss or xvss as the ground return line. pvdd supply auxiliary pin for analog circ uitry. this pin has to be connected via a 3 nf capacitor to avdd1. extra care should be taken to achieve a low-inductance pcb line. avdd0/avss0 supply supply for analog output amplifier. avdd1/avss1 supply supply for internal analog circuits (a/d, d/a convert- ers, clock, pll, s/pdif input). avdd0/avss0 and avdd1/avss1 should receive the same supply voltages. 4.3.2. analog reference pins agndc internal analog reference voltage. this pin serves as the internal ground connection for the analog circuitry. vref analog reference ground. all analog inputs and out- puts should drive their return currents using separate traces to a ground starpoint close to this pin. connect to avss1. this reference pin should be as noise-free as possible. 4.3.3. dc/dc converters and battery voltage supervision dcsg1/dcsg2 supply dc/dc converters switch ground. connect using sep- arate wide trace to negative pole of battery cell. con- nect also to avss0/1 and vss/xvss, vref. dcso1/dcso2 supply dc/dc converter switch connection. if the respective dc/dc converter is not used, this pin must be left vacant. vsens1/vsens2 in sense input and power output of dc/dc converters. if the respective dc/dc converter is not used, this pin should be connected to a supply to enable proper function of the pup-signals. dcen in enable signal for both dc/dc converters. if none of the dc/dc converters is used, this pin must be con- nected to vss. pup out power-up. this signal is set when the required volt- ages are available at both dc/dc converter output pins vsens1 and vsens2. the signal is cleared when both voltages have dropped below the reset level in the dccf register. vbat in analog input for battery voltage supervision. 4.3.4. oscillator pins and clocking xti in xto out the xti pin is connected to the input of the internal crystal oscillator, the xto pi n to its output. each pin should be directly connected to the crystal and to a ground-connected capacitor (see application diagram, fig. 5?1 on page 87). clko out the clko can drive an output clock line. 4.3.5. control lines i2cc scl in/out i2cd sda in/out standard i 2 c control lines. dvs in i 2 c device address selector. connect this pin either to vdd (i 2 c device address: 3e/3f hex ) or vss (i 2 c device address: 3c/3d hex ) to select a proper i 2 c device address (see also table 3?2 on page 23). 4.3.6. parallel interface lines pi12..pi19 in/out the pio input pins pi12..pi19 are used as 8-bit i/o interface to a microcontroller in order to transfer com- pressed and uncompressed data. pi12 is the lsb, pi19 the msb. mas 35x9f data sheet 60 june 30, 2004; 6251-505-1ds micronas 4.3.6.1. pio handshake lines pcs in the pio chip select pcs must be set to ?0? to activate the pio in operation mode. pr in pin pr must be set to ?1? to validate data output from mas 35x9f pio pins. prtr out ready to read. this signal indicates that the mas 35x9f is able to receive data in pio input mode. prtw out ready to write. this pin indicates that mas 35x9f has data available for pio output mode. eod out eod indicates the end of an dma cycle in the ic?s pio input mode. in ?serial? input mode it is used as demand signal, that indicates that new input data are required. 4.3.7. serial input interface (sdi) sid data in/out sii word strobe in/out sic clock in/out i 2 s compatible serial interface a for digital audio data. in the standard firmware this interface is not used. note: please refer to bit [0] of table 3?6 4.3.8. serial input interface b (sdib) sibd data in sibi word strobe in sibc clock in the serial interface b is primarily used as bitstream input interface. the sibi line must be connected to vss in the standard application. 4.3.9. serial output interface (sdo) sod data out soi word strobe out soc clock in/out data, frame indication, and clock line of the serial output interface. the soi is reconfigurable and can be adapted to several i 2 s compliant modes. 4.3.10. s/pdif input interface spdi1 in spdi2 in spdir in spdif1 and spdif2 are alternative input pins for s/pdif sources according to the iec 958 consumer specification are used in conjunction with download software only. a switch at d0:ff6 selects one of these pins at a time. the spdir pin is a common reference for both input lines (see fig. 5?1 on page 87). 4.3.11. s/pdif output interface spdo out the spdo pin provides an digital output with standard cmos level that is compliant to the iec 958 consumer specification. 4.3.12. analog input interfaces in the standard mpeg-decoding dsp firmware the analog inputs are not used. however, they can be selected as a source for the d/a converters (set mix adc scale of the d/a converter source mixer, register 00 06 hex in table 3?16). micin in micbi in the micin input may be directly used as electret microphone input, which should be connected as described in application information (see fig. 5?1 on page 87). the micbi signal provides the supply volt- age for these microphones. inl in inr in inl and inr are analog line-in input lines. they are connected to the embedded stereo a/d converter of the mas 35x9f. the sources should be ac-coupled. the reference ground for these analog input pins is the vref pin. 4.3.13. analog output interfaces outl out outr out outl and outr are left and right analog outputs, that may be directly connected to the headphones as described in the application information (see fig. 5?1 on page 87). filtl in filtr in connection to input terminal of output amplifier.can be used to connect a capacitance from outl respectively outr to filtl respectively filtr in parallel to feed- back resistor and thus implement a low pass filter to reduce the out-of-band noise of the dac. data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 61 4.3.14. miscellaneous sync out the sync signal indicates the detection of a frame start in the input data of mas 35x9f. usually this sig- nal generates an interrupt in the controller. por in the power-on reset pin is used to reset the whole mas 35x9f. the por is an active-low signal (see fig. 5?1 on page 87). te in the te pin is for production test only and must be con- nected with vss in all applications. 4.4. pin configuration fig. 4?4: plqfp64-1/pmqfp64-2 and pqfn64-1 package sibd sibc sibi spdi2 spdi1 spdir filtl avdd0 outl outr avss0 filtr avss1 vref pvdd avdd1 pr prtw prtr eod pup vbat sync i2cd i2cc clko dcen vsens2 dcso2 dcsg2 dcsg1 dcso1 sic sii sid soc soi sod pi12 spdo pi13 pi14 pi15 pi16 pi17 pi18 pi19 pcs micin micbi inl inr te xti xto agndc por vss xvss vdd xvdd i2cvdd dvs vsens1 mas 35x9f 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 mas 35x9f data sheet 62 june 30, 2004; 6251-505-1ds micronas 4.5. internal pin circuits fig. 4?5: input pins pcs , pr fig. 4?6: input pin te, dvs, por fig. 4?7: input pin dcen fig. 4?8: input/output pins soc, soi, sod, pi12...pi19, spdo fig. 4?9: input pins sic, sii, sid fig. 4?10: input/output pins i2cc, i2cd fig. 4?11: input/output pins dcso1/2, dcsg1/2, vsens1/2 fig. 4?12: output pins prtw , eod , prtr , clko, sync, pup fig. 4?13: clock oscillator xti, xto ttlin xvdd p n xvss xvdd p n xvss vdd n vss dcso dcsg vsens n p xvdd xvss n p avdd avss p p p n n n xto xti enable data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 63 fig. 4?14: analog input pins micin, inl, inr fig. 4?15: microphone bias pin (micbi) fig. 4?16: analog outputs outl(r) and connections for filter capacitors filtl(r) fig. 4?17: analog ground generation with pin to connect external capacitor fig. 4?18: s/pdif inputs fig. 4?19: battery voltage monitor vbat 4.5.1.reset pin configuration for mas 3529f and mas 3539f the power-on reset pin por is used to reset the entire mas 35x9f. the por is an active-low signal. note: if a pull-up resistor is used for building a delay time here (see fig. 5?1 on page 87), referred to the vdd pins, the maximum allowed value for this resistor is 3.3 kohm! ? ? ? i 1.25 v ? ? ? = mas 35x9f data sheet 64 june 30, 2004; 6251-505-1ds micronas 4.6. electrical characteristics abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip 4.6.1. absolute maximum ratings stresses beyond those listed in the ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these conditions is not implied. exposure to absolute maximum rating conditions for extended periods will affect device reliability. this device contains circuitry to protect the inputs and ou tputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso- lute maximum-rated voltages to this high-impedance circuit. all voltages listed are referenced to ground (v sup1, v sup2, v sup3 = 0 v) except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. do not insert the device into a live socket. instead, apply power by switching on the external power supply. for power up/down sequences, see the instructions in section 2.6. of this document. table 4?1: absolute maximum ratings symbol parameter pin name limit values unit min. max. t a 1) ambient temperature - operating conditions - extended temperature range 1) ? ? ? ? ? ? ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 65 v sup2 supply voltage 2 vdd, xvdd, i2cvdd, avdd0/1 1) ? ? ? ? ? ? ? ? ? table 4?1: absolute maximum ratings, continued symbol parameter pin name limit values unit min. max. mas 35x9f data sheet 66 june 30, 2004; 6251-505-1ds micronas 4.6.1.1. recommended operating conditions functional operation of the device beyond those indicated in the ?recommended operating conditions/characteris- tics? is not implied and may result in unpredictable behavior , reduce reliability and lifetime of the device. all voltages listed are referenced to ground (v sup1, v sup2, v sup3 = 0 v) except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. do not insert the device into a live socket. instead, apply power by switching on the external power supply. for power up/down sequences, see the instructions in section section 2.11.2. of this document. symbol parameter pin name limit values unit min. typ. max. t a ambient operating temperature plqfp64-1 pmqfp64-2 pqfn64-1 0 0 0 25 25 25 1) 85 85 85 / mp3 decoder and sd decryption/aac decoder) 2.5 2.7 3.6 v supi2c i 2 c bus supply voltage i2cvdd v supdn 2) at vdd 3.9 v v supx pin supply voltage xvdd 2.2 2.5 3.6 v pin supply voltage in relation to digital supply voltage 0.62 * v supdn 2) 1.6 * v supdn 2) v v supa analog audio supply voltage avdd0/1 2.2 2.7 3.6 v analog audio supply voltage in rela- tion to the digital supply voltage 0.62 * v supdn 2) 1.6 * v supdn 2) v v supdx voltage differences within supply domains v 1) a power-optimized board layout is recommended. the case operating temperatures mentioned in the ?recommended operating conditions? must not be exceeded at worst case conditions of the application. for turn-on voltage of dsp and codec, please refer to section 2.11.2.1. 2) n = 1 or 2 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 67 table 4?2: input clock frequency symbol parameter pin name limit values unit min. typ. max. f clk 1) g.729 decoder g.729 encoder xti, xto 16.4 13.7 mhz mhz mpeg decoder (sc4 en- decoder) 11.0 mhz 1) minimum f clk for sd-card decryption is defined in a supplement. table 4?3: input levels symbol parameter pin name limit values unit min. typ. max. v il input low voltage i2cc, i2cd 0.3 v v ih input high voltage 1.4 v v il input low voltage por , dcen 0.2 v v ih input high voltage 0.9 v v ild input low voltage pi, si(b)i, si(b)c, si(b)d, pr, pcs , te, dvs 0.3 v v ihd input high voltage v supx ? mas 35x9f data sheet 68 june 30, 2004; 6251-505-1ds micronas table 4?4: analog input and output recommendations symbol parameter pin name limit values unit min. typ. max. analog reference c agndc1 analog filter capacitor agndc 1.0 3.3 f c agndc2 ceramic capacitor in parallel 10 nf c pvdd capacitor for analog circuitry pvdd 3 nf analog audio inputs c inad dc-decoupling capacitor at a/d- converter inputs inl/r 390 nf c inmi dc-decoupling capacitor at microphone-input micin 390 nf c lmicbi minimum-capacitance at micro- phone bias micbi 3.3 nf analog audio filter outputs c filt filter capacitor for headphone amplifier high-q type, np0 or c0g material filtl/r outl/r ? analog audio output z aol_hp analog output load with stereo headphones outl/r 16 ? dc/dc-converter external circuitry (please refer to application example) c 1 vsens blocking (<100 m ? s/pdif interface analog input c spi s/pdif coupling capacitor spdi1/2 spdir 100 nf data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 69 4.6.2. digital characteristics at t = t a , v supd , v supa = 2.2 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a =25 symbol parameter pin name limit values unit test conditions min. typ. max. digital supply voltage i supd current consumption vdd, xvdd, i2cvdd 36 ma 2.2 v, sampling fre- quency digital outputs and inputs o digl output low voltage pi, soi, soc, sod, eod , prtr , prtw , clko, sync, pup, spdo 0.3 v i load = 2 ma o digh output low voltage v supx ? ? ? mas 35x9f data sheet 70 june 30, 2004; 6251-505-1ds micronas 4.6.2.1. i 2 c characteristics at t = 25 fig. 4?20: i 2 c timing diagram symbol parameter pin name limit values unit test conditions min. typ. max. i 2 c input specifications f i2c upper limit i 2 c bus frequency operation i2cc 400 khz t i2c1 i 2 c start condition setup time i2cc, i2cd 300 ns t i2c2 i 2 c stop condition setup time i2cc, i2cd 300 ns t i2c3 i 2 c clock low pulse time i2cc 1250 ns t i2c4 i 2 c clock high pulse time i2cc 1250 ns t i2c5 i 2 c data setup time before rising edge of clock i2cc 80 ns t i2c6 i 2 c data hold time after falling edge of clock i2cc 80 ns v i2col i 2 c output low voltage i2cc, i2cd 0.4 v i load = 3 ma i i2coh i 2 c output high leakage current i2cc, i2cd 1 a t i2col1 i 2 c data output hold time after falling edge of clock i2cc, i2cd 20 ns t i2col2 i 2 c data output setup time before rising edge of clock i2cc, i2cd 250 ns f i2c = 400 khz v i2cil i 2 c input low voltage i2cc, i2cd 0.3 v supi2c v i2cih i 2 c input high voltage i2cc, i2cd 0.6 v supi2c t w wait time i2cc, i2cd 0 0.5 4 ms i2cc i2cd as input i2cd as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t ic2ol1 h l h l h l data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 71 4.6.2.2. serial (i 2 s) input interface characteristics (sdi, sdib) at t = t a , v supd , v supa = 2.2 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a =25 fig. 4?21: continuous data stream at serial input a or b. in this mode, the word strobe si(b)i is not used and the data are read at the fallin g edge of the clock (bit[2] in d0:346 is set). symbol parameter pin name limit values unit test conditions min. typ. max. t siclk i 2 s clock input clock period si(b)c 325 ns f s = 48 khz stereo, 32 bits per sample (for demand mode see ta b l e 4 ? 5 ) t sids i 2 s data setup time before rising edge of clock (for continuous data stream: falling edge) si(b)c, si(b)d 50 ns t sidh i 2 s data hold time si(b)d 50 ns t siis i 2 s ident setup time before rising edge of clock (for continuous data stream: falling edge) si(b)c, si(b)i 50 ns t siih i 2 s ident hold time si(b)i 50 ns t bw burst wait time si(b)c, si(b)d 480 table 4?5: maximum allowed samp le clock frequency in demand mode f sample (khz) f c (mhz) min. t siclk (ns) 48, 32 6.144 162 44.1 5.6448 177 24, 16 3.072 325 22.05 2.8224 354 12, 8 1.536 651 11.025 1.4112 708 h l h l h l t siclk t sidh t sids si(b)c si(b)i si(b)d mas 35x9f data sheet 72 june 30, 2004; 6251-505-1ds micronas fig. 4?22: serial input of i 2 s signal 4.6.2.3. serial output interface characteristics (sdo) at t = t a , v supd , v supa = 2.2 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a =25 table 4?6: allowed transmission delays of external data source mpeg1/2 layer 2/3 symbol parameter pin name limit values unit test conditions min. typ. max. t start48-320 allowed delay time before start of serial data transmission after assertion of signal at eod eod 3.1 ms 48 khz/s, 320 kbit/s t start48-64 5.7 ms 48 khz/s, 64 kbit/s t start24-320 4.2 ms 24 khz/s, 320 kbit/s t start24-32 9.2 ms 24 khz/s, 32 kbit/s t start12-64 23.1 ms 12 khz/s, 64 kbit/s t start12-16 25.6 ms 12 khz/s, 16 kbit/s t start8-64 34.8 ms 8 khz/s, 64 kbit/s t start8-8 38.4 ms 8 khz/s, 8 kbit/s t stop allowed delay time before stop of serial data transmission after deassertion of signal at eod eod 1.3 ms clock rate of input data 1mbit/s symbol parameter pin name limit values unit test conditions min. typ. max. t soclk i 2 s clock output frequency soc 325 ns f s = 48 khz stereo 32 bits per sample t soiss i 2 s word strobe delay time after falling edge of clock soc, soi 0ns t soodc i 2 s data delay time after falling edge of clock soc, sod 0ns h l h l h l t siclk t sidh t sids t siih t siis si(b)c si(b)i si(b)d data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 73 fig. 4?23: serial output interface timing fig. 4?24: sample timing of the sdo interface in 16 bit/sample mode d0:346 settings are bit[14] = 0 (soc not inverted) bit[11] = 1 (soi delay) bit[5] = 0 (word strobe not inverted) bit[4] = 1 (16 bits/sample) fig. 4?25: sample timing of the sdo interface in 32 bit/sample mode d0:346 settings are bit[14] = 0 (soc not inverted) bit[11] = 0 (no soi delay) bit[5] = 1 (word strobe inverted) bit[4] = 0 (32 bits/sample) h l h l h l t soclk t soiss t soiss t soodc soc soi sod soc sod v h v l soi left 16-bit audio sample right 16-bit audio sample 15141312111098 76543210 13 12 11 10 9 8 76543210 15 14 v h v l v h v l 302928272625...76543210 31302928272625 76543210 left 32-bit audio sample right 32-bit audio sample soc sod soi v h v l v h v l v h v l ... ... 31 ... mas 35x9f data sheet 74 june 30, 2004; 6251-505-1ds micronas 4.6.2.4. s/pdif input characteristics at t = t a , v supd , v supa = 2.2 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a =25 fig. 4?26: timing of the s/pdif input symbol parameter pin name limit values unit test conditions min. typ. max. v s signal amplitude spdi1, spdi2, spdir 200 500 1000 mv pp f s1 bi-phase frequency spdi1, spdi2, spdir 2.048 mhz data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 75 4.6.2.5. s/pdif output characteristics at t = t a , v supd , v supa = 2.2 ... 3.6 v, f crystal = 18.432 mhz, typ. values for t a =25 fig. 4?27: timing of the s/pdif output 4.6.2.6. pio as parallel input interface: dma mode in decoding mode, the data transfer can be started after the eod pin of the mas 35x9f is set to ?high?. after verifying this, the controller signalizes the send- ing of data by activating the pr line. the mas 35x9f responds by setting the rtr line to the ?low? level. the mas 35x9f reads the data pi[19:12] and sets rtr to low after rising edge of pr. after rtr is set to high, the mc sets pr to low. the next data word write oper- ation will be initialized again by setting the pr line via the controller. please refer to figure for the exact tim- ing. the procedure above will be repeated until the mas 35x9f sets the eod signal to ?0? which indicates that the transfer of one data block has been executed. subsequently, the controller should set pr to ?0?, wait until eod rises again and then repeat the procedure to send the next block of data. the dma buffer for mpeg decoding is 30 bytes long. the size for g.729 is 10 bytes. symbol parameter pin name limit values unit test conditions min. typ. max. f s1 bi-phase frequency spdo 3.072 mhz f s = 48 khz f s2 bi-phase frequency spdo 2.822 mhz f s = 44.1 khz f s3 bi-phase frequency spdo 2.048 mhz f s = 32 khz t p bi-phase period spdo 326 ns at f s = 48 khz, (highest sampling rate) t r rise time spdo 0 2 ns c load =10pf t f fall time spdo 0 2 ns c load =10pf duty cycle spdo 50 % t h1,l1 spdo 163 ns minimum/maximum pulse duration with a level above 90% or below 10% and at f s =48khz t h0,l0 spdo 326 ns minimum/maximum pulse duration with a level above 90% or below 10% and at f s =48khz v s signal amplitude spdo v supd t p t r t f bit value = 1 bit value = 0 t h1 t l1 t h0 t l0 mas 35x9f data sheet 76 june 30, 2004; 6251-505-1ds micronas fig. 4?28: handshake protocol for writing mpeg data to the pio-dma table 4?7: pio input dma mode timing symbol pin name min. max. t st pr, eod 10 ns 2000 table 4?8: t_clm in mp3 sample rate [khz] t_clm [ns] f_clm [mhz] 48 or 32 41 24.5760 44.1 44 22.5792 24 or 16 81 12.2880 22.05 89 11.2896 12 or 8 163 6.1440 11.025 177 5.6448 table 4?9: t_clm in aac sample rate [khz] t_clm [ns] f_clm [mhz] 48 or 32 33 30.720 44.1 35 28.224 24 or 16 65 15.360 22.05 71 14.112 12 or 8 130 7.680 11.025 142 7.056 customer ic /eod pr /rtr pi(19:12) gpio gpio d7-d0 tset 1 = tchl_dov th tr trtrq tst /cs /wr twrh _csh tset 2 tpr = twr trpr teod teodq mas3509f /eod pr /rtr pi(19:12) data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 77 4.6.2.7. pio as parallel input interface: program download mode handshake for pio input in program download mode is accomplished through the rtr, pcs, and pi12..pi19 signal lines (see fig. 4?29). the pr line should be set to low level. the mas 35x9f will drive rtr low as soon as it is ready to receive a byte and rtr will stay low until one byte has been written. writing of a byte is performed with a pcs pulse, driven by the microcontroller. the mas 35x9f reads data afte r the falling edge of pcs and will finish the cycle by setting rtr to high level after the rising edge of pcs. the next data transfer is initialized by the mas 35x9f by driving the rtr line. fig. 4?29: pio program download mode timing table 4?10: pio program download mode timing symbol pin min. max. unit t 0 rtr , pcs 0 mas 35x9f data sheet 78 june 30, 2004; 6251-505-1ds micronas 4.6.2.8. pio as parallel output interface some downloadable software may use the pio inter- face (lines pi19...pi12) as output. the data transfer rate and conditions are defines by the software func- tion. handshaking for pio output mode is accomplished through the rtw , pcs , and pi12..pi19 signal lines (see fig. 4?30). the pr line has to be set to high level. rtw will go low as soon as a byte is available in the output buffer and will stay low until a byte has been read. reading of a byte is performed with a pcs pulse. data is latched out from the mas on the falling edge of pcs and removed from the bus on the rising edge of pcs . fig. 4?30: output timing table 4?11: pio output mode timing symbol pin min. max. unit t 0 rtw , pcs 0.010 1800 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 79 4.6.3. analog characteristics at t = t a , v supdn , v supx = 2.2 to 3.6 v, v supa = 2.2 to 3.6 v, f crystal = 13 to 20 mhz, typical values at t a =25 symbol parameter pin name limit values unit test conditions min. typ. max. analog supply i avdd current consumption analog audio avdd0/1 5 ma v supa = 2.2 v, mute i qosc current consumption crystal oscillator avdd0/1 200 crystal oscillator v dcclk dc voltage at oscillator pins xti, xto 0.5 v supa v aclk clock amplitude 0.5 v supa ? ? analog reference v agndc analog reference voltage agndc v r l >> ?, ? mas 35x9f data sheet 80 june 30, 2004; 6251-505-1ds micronas analog audio input v ai analog line input clipping level (at minimum analog input gain, i.e. ? ? ? ? ? ? ? ? ? ? ? symbol parameter pin name limit values unit test conditions min. typ. max. data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 81 audio output v ao1 analog output voltage ac outl/r r l ? dv ao1 deviation of dc-level at analog output for agndc- voltage outl/r ? mv v ao2 analog output voltage ac outl/r r l is 16 ? ? ? ? ? ? ? ? ? symbol parameter pin name limit values unit test conditions min. typ. max. mas 35x9f data sheet 82 june 30, 2004; 6251-505-1ds micronas 4.6.4. dc/dc converter characteristics at t = t a , v in =1.2v, v outn =3.0v, f clk = 18.432 mhz, f sw = 384 khz, pwm mode, l = 22 ? ? symbol parameter pin name limit values unit test conditions min. typ. max. symbol parameter pin name limit values unit test conditions min. typ. max. v in minimum start-up input voltage 0.9 v i load ?4 ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 83 i suppfm1 supply current in pfm mode vsens1 75 a 3) i suppfm2 vsens2 135 i suppwm1 supply current in pwm mode vsens1 265 a vsensn 3) 4) i suppwm2 vsens2 325 i lnmax nmos switch current limit (low side switch) dcson, dcsgn 1 a pwm-mode 0.4 a pfm-mode i iptoff pmos switch turnoff current (rectifier switch) dcson vsensn 70 ma r on nmos switch on resistance (low side switch) dcso1, dcsg1 170 m ? ? 0.4 symbol parameter pin name limit values unit test conditions min. typ. max. mas 35x9f data sheet 84 june 30, 2004; 6251-505-1ds micronas 4.6.5. typical performance characteristics fig. 4?31: efficiency vs. load current efficiency vs. load current dcdc1 (v out =3.5v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? efficiency vs. load current dcdc1 (v out =3.0v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? efficiency vs. load current dcdc2 (v out =3.5v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? efficiency vs. load current dcdc2 (v out =3.0v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 85 fig. 4?32: maximum load current vs. input voltag note : efficiency is measured as v sensn efficiency vs. load current dcdc1 (v out =2.2v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? maximum load current maximum load current (a) input voltage (v) 0.8 0.6 0.4 0.2 0 0.0 1.0 2.0 3.0 vs. input voltage v out : 2.2 v 3.0 v 3.5 v pfm pwm dcdc1 efficiency vs. load current dcdc2 (v out =2.2v) efficiency (%) load current (a) 100 80 60 40 20 0 10 ? ? ? ? maximum load current maximum load current (a) input voltage (v) 0.8 0.6 0.4 0.2 0 0.0 1.0 2.0 3.0 vs. input voltage v out : 2.2 v 3.0 v 3.5 v pfm pwm dcdc2 mas 35x9f data sheet 86 june 30, 2004; 6251-505-1ds micronas loadregulation at v out = 2.7 v, 2.5 v output voltage (v) load current (ma) 2.75 2.6 2.55 2.5 2.45 2.4 0 50 100 150 v in : 1.5 v 1.2 v 0.9 v dcdc1 200 1.5 v 0.9 v 2.7 2.65 no-load battery current v out =3.0v battery current (ma) input voltage (v) 10 4 2 0 0.5 1.0 1.5 2.0 2.5 both dcdc running in pwm one dcdc running in pfm 8 6 3.0 loadregulation at v out = 3.0 v, 3.5 v output voltage (v) load current (ma) 3.55 3.4 3.05 3.0 2.95 2.9 0 50 100 150 v in : 1.5 v 1.2 v 0.9 v dcdc1 200 1.5 v 0.9 v 3.5 3.45 data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 87 5. application 5.1. typical application in a portable player ? ? fig. 5?1: application circuit of the mas 35x9f. for connections of the dc/dc converters, please refer to fig. 5?2. sibd sibc sibi spdi2 spdi1 spdir filtl avdd0 outl outr avss0 filtr avss1 vref pvdd avdd1 pr prtwq prtrq eodq pup vbat sync i2cd i2cc clko dcen vsens2 dcso2 dcsg2 dcsg1 dcso1 micin micbi inl inr te xti xto agndc por vss xvss vdd xvdd i2cvdd dvs vsens1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pcsq pi19 pi18 pi17 pi16 pi15 pi14 pi13 pi12 sod soi soc sid sii sic spdo 470p 470p 3n 10n 22u 3u3 10n 100n 220p 1n 1.5u 4u7 18.432 mhz 1n 1.5u d a d a vdc1 18p 18p 5 4k7 4k7 vdc2 220u 220u 22 22 75 75 100 100 1.5k 1.5k 6.8n 6.8n a 100n 100n 390n 390n 390 n a 390p 390p 3.6...5.6 k mic lr headphone > 16 ? s mart m edia c ard pio-control mpeg, celp, sc4 see figure caption c vdc2 tape recorder fm radio vdc2 vdc2 vdc2 option for reference clock place vdd / xvdd -filter capacitors above ground plane <3.3 kohm a d star point dcsg1 and dcsg2 ground connection d d d 10k place all ceramic capacitors as close as possible to ic pins 470p capacitorss should be high-q (np0 or c0g) very close to pins i 2 c-address connect to vss or i2cvdd telephone separate trace vdc1 3.3 n 100 k 1u d mas 35x9f see note on page 69 mas 35x9f data sheet 88 june 30, 2004; 6251-505-1ds micronas 5.2. recommended dc/dc converter application circuit (power optimized scenario, (see fig. 2?7 on page 13)). fig. 5?2: external circuitry for the dc/dc converters for turn-on voltage of dsp and codec, please refer to section 2.11.2.1. mas 35x9f v in (input voltage) vdc2 d2, schottky dcsg2 dcso2 l2 = 22 h dcen vsens2 e.g. 3.0 v for c, (0.9..1.5 v) storage media + power-on push button c2 = 330 f (low esr) vdc1 d1, schottky dcsg1 vss, xvss dcso1 l1 = 22 h vsens1 e.g. 2.2 v + c3 = 330 f (low esr) + c1 = 330 f vbat d avss0/1 a a d avdd0/1 very close to pins star point dcsg1 and dcsg2 ground connection v ref data sheet mas 35x9f micronas june 30, 2004; 6251-505-1ds 89 all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. mas 35x9f data sheet 90 june 30, 2004; 6251-505-1ds micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-505-1ds 6. data sheet history 1. preliminary data sheet: ?mas 35x9f, mpeg layer 2/3, aac audio decoder, g.729 annex a codec?, aug. 01, 2001, 6251-505-1pd. first release of the preliminary data sheet. 2. data sheet: ?mas 35x9f mpeg layer 2/3, aac audio decoder, g.729 annex a codec?, june 30, 2004, 6251-505-1ds. first release of the data sheet. major changes: ? new package diagrams were included for plqfp64-1, pmqf p64-2, pqfn64-1 ? functional description of the mp3 block input mode now available for improved input timing behavior of the mpeg 1/2/2.5 layer3 decoder ? important advice for turn-on and operating voltage ? changes in configuration registers ? tables were added: pio input dma mode timing; sample rate in mp3; sample rate in aac ? handshake protocol for writing mpeg data to the pio-dma was added. |
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